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ADRF6520ACPZ-R7 数据表(PDF) 7 Page - Analog Devices |
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ADRF6520ACPZ-R7 数据表(HTML) 7 Page - Analog Devices |
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7 / 29 page ![]() Data Sheet ADRF6520 Rev. 0 | Page 7 of 29 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 OPP1 23 OPM1 22 COM 21 VGN1 20 VGN2 19 COM 18 OPM2 17 OPP2 1 2 3 4 5 6 7 8 INP1 INM1 COM CFLT1 CFLT2 COM INM2 INP2 ADRF6520 TOP VIEW (Not to Scale) NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW IMPEDANCE GROUND PAD. Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1, 2 INP1, INM1 Channel 1 Differential Inputs, 100 Ω Differential Input Impedance. 3, 6, 19, 22 COM Analog Common. Connect COM to an external circuit common using the lowest possible impedance. 4, 5 CFLT1, CFLT2 Averaging Capacitors for RMS Detectors. The user can leave these pins open for the fastest response time and the least amount of rms averaging. 7, 8 INM2, INP2 Channel 2 Differential Inputs, 100 Ω Differential Input Impedance. 9 RST SPI Reset to Default Bit Values. This pin is active low. Pull the pin high under nonactive conditions. The transistor-transistor logic (TTL) levels are VLOW < 0.8 V and VHIGH > 2 V. 10 SCLK SPI Port Clock. The TTL levels are VLOW < 0.8 V and VHIGH > 2 V. 11 SDIO SPI Data Input and Output. The TTL levels are VLOW < 0.8 V and VHIGH > 2 V. 12, 13, 28, 29 VPS Analog Positive Supply Voltage: 3.15 V to 3.45 V. 15, 26 CHP2, CHP1 DC Offset Correction Loop Capacitors. Connect the capacitors to a circuit common. 16 VRMS RMS Detector Output. The output transfer function is 1 V/V rms × (CH1_RMS + CH2_RMS), where CH1_RMS is the differential rms voltage of the input of the Channel 1 filter, and CH2_RMS is the differential rms voltage of the input of the Channel 2 filter. The user can leave the pin open if not using the rms detector; there is no need to terminate this pin. Load this pin with at least 1 kΩ to ground; values lower than this prevent the detector output from reaching its full-scale value. 17, 18 OPP2, OPM2 Channel 2 Differential Outputs. These outputs have a 20 Ω differential output impedance. 20, 21 VGN2, VGN1 VGA2 and VGA1 Analog Gain Control. These pins operate from 0 V to 1.5 V with 30 mV/dB gain scaling. 23, 24 OPM1, OPP1 Channel 2 Differential Outputs. These outputs have a 20 Ω differential output impedance. 25 ENBL Chip Enable. Pull this pin high to enable the chip. Voltages on ENBL of less than 1.6 V disable the device. 30 COMD Digital Common. Connect this pin to an external circuit common using the lowest possible impedance. 31 VPSD Digital Positive Supply Voltage: 3.15 V to 3.45 V. 32 CS Chip Select Bar to Enable SPI Programming. CS is an SPI programming pin and is active low. The TTL levels are VLOW < 0.8 V and VHIGH > 2 V. EP Exposed Ground Pad. Connect the exposed pad to a low impedance ground pad. |
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