ADAU1361BCPZ-R7 datasheet(4/80 Pages) AD

4 / 80 page

ADAU1361

Data Sheet

Rev. D | Page 4 of 80

SPECIFICATIONS

Supply voltage (AVDD) = 3.3 V, TA = 25°C, master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement

bandwidth = 20 Hz to 20 kHz, word width = 24 bits, CLOAD (digital output) = 20 pF, ILOAD (digital output) = 2 mA, VIH = 2 V, VIL = 0.8 V,

unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase

deviation specifications.

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at 25°C (ambient).

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC performance excludes mixers

and PGA

ADC Resolution

All ADCs

Bits

Digital Attenuation Step

0.375

Digital Attenuation Range

INPUT RESISTANCE

Single-Ended Line Input

−12 dB gain

kΩ

0 dB gain

kΩ

6 dB gain

10.5

kΩ

PGA Inverting Inputs

−12 dB gain

84.5

kΩ

0 dB gain

kΩ

35.25 dB gain

kΩ

PGA Noninverting Inputs

All gains

105

kΩ

SINGLE-ENDED LINE INPUT

Full-Scale Input Voltage (0 dB)

Scales linearly with AVDD

AVDD/3.3

V rms

AVDD = 1.8 V

0.55 (1.56)

V rms (V p-p)

AVDD = 3.3 V

1.0 (2.83)

V rms (V p-p)

Dynamic Range

20 Hz to 20 kHz, −60 dB input

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

No Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

Total Harmonic Distortion + Noise

−1 dBFS

AVDD = 1.8 V

−88

AVDD = 3.3 V

−90

Signal-to-Noise Ratio

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

No Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

Gain per Step

Total Gain Range

−12

Mute Attenuation

−87

Interchannel Gain Mismatch

0.005

Offset Error

Gain Error

−12

Interchannel Isolation

Power Supply Rejection Ratio

CM capacitor = 20 μF

100 mV p-p @ 217 Hz

100 mV p-p @ 1 kHz

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