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ADAU1361BCPZ-R7 数据表(PDF) 43 Page - Analog Devices |
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ADAU1361BCPZ-R7 数据表(HTML) 43 Page - Analog Devices |
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43 / 80 page ![]() Data Sheet ADAU1361 Rev. D | Page 43 of 80 LRCLK BCLK SDATA MSB LEFT CHANNEL LSB MSB RIGHT CHANNEL LSB 1/ fS Figure 57. I2S Mode—16 Bits to 24 Bits per Channel LRCLK BCLK SDATA LEFT CHANNEL MSB LSB MSB RIGHT CHANNEL LSB 1/ fS Figure 58. Left-Justified Mode—16 Bits to 24 Bits per Channel LRCLK BCLK SDATA LEFT CHANNEL MSB LSB MSB RIGHT CHANNEL LSB 1/ fS Figure 59. Right-Justified Mode—16 Bits to 24 Bits per Channel LRCLK BCLK SDATA SLOT 0 SLOT 2 32 BCLKs MSB MSB – 1 MSB – 2 128 BCLKs SLOT 1 SLOT 3 LRCLK BCLK SDATA Figure 60. TDM 4 Mode LRCLK SLOT 0 SLOT 1 SLOT 2 SLOT 3 CH 0 BCLK SDATA 32 BCLKs MSB TDM Figure 61. TDM 4 Mode with Pulse Word Clock |
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