 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADAU1361BCPZ-R7 数据表(PDF) 15 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADAU1361BCPZ-R7 数据表(HTML) 15 Page - Analog Devices |
|
|
15 / 80 page  Data Sheet ADAU1361 Rev. D | Page 15 of 80 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 IOVDD 2 MCLK 3 ADDR0/CLATCH 4 JACKDET/MICIN 5 MICBIAS 6 LAUX 7 CM 8 AVDD 24 DVDDOUT 23 AVDD 22 AGND 21 MONOOUT 20 LHP 19 RHP 18 LOUTP 17 LOUTN TOP VIEW (Not to Scale) ADAU1361 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1361 GROUNDS. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 7. Pin Configuration Table 10. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 IOVDD PWR Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD, which also sets the highest input voltage that should be seen on the digital input pins. IOVDD should be set between 1.8 V and 3.3 V. The current draw of this pin is variable because it is dependent on the loads of the digital outputs. IOVDD should be decoupled to DGND with a 100 nF capacitor and a 10 μF capacitor. 2 MCLK D_IN External Master Clock Input. 3 ADDR0/CLATCH D_IN I2C Address Bit 0 (ADDR0). SPI Latch Signal (CLATCH). Must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction can take a different number of CCLKs to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction. 4 JACKDET/MICIN D_IN Detect Insertion/Removal of Headphone Plug (JACKDET). Digital Microphone Stereo Input (MICIN). 5 MICBIAS A_OUT Bias Voltage for Electret Microphone. 6 LAUX A_IN Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2. 7 CM A_OUT AVDD/2 V Common-Mode Reference. A 10 μF to 47 μF standard decoupling capacitor should be connected between this pin and AGND to reduce crosstalk between the ADCs and DACs. This pin can be used to bias external analog circuits, as long as they are not drawing current from CM (for example, the noninverting input of an op amp). 8 AVDD PWR 1.8 V to 3.65 V Analog Supply for DAC and Microphone Bias. This pin should be decoupled locally to AGND with a 100 nF capacitor. 9 AGND PWR Analog Ground. The AGND and DGND pins can be tied together on a common ground plane. AGND should be decoupled locally to AVDD with a 100 nF capacitor. 10 LINP A_IN Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2. 11 LINN A_IN Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2. 12 RINP A_IN Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2. 13 RINN A_IN Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2. 14 RAUX A_IN Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2. 15 ROUTP A_OUT Right Line Output, Positive. Biased at AVDD/2. 16 ROUTN A_OUT Right Line Output, Negative. Biased at AVDD/2. 17 LOUTN A_OUT Left Line Output, Negative. Biased at AVDD/2. 18 LOUTP A_OUT Left Line Output, Positive. Biased at AVDD/2. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
