ADAU1361BCPZ-R7 datasheet(60/80 Pages) AD

60 / 80 page

ADAU1361

Data Sheet

Rev. D | Page 60 of 80

R19: ADC Control, 16,409 (0x4019)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

ADCPOL

HPF

DMPOL

DMSW

INSEL

ADCEN[1:0]

Table 46. ADC Control Register

Bits

Bit Name

Description

ADCPOL

Invert input polarity.

0 = normal (default).

1 = inverted.

HPF

ADC high-pass filter select. At 48 kHz, f3dB = 2 Hz.

0 = off (default).

1 = on.

DMPOL

Digital microphone data polarity swap.

0 = invert polarity.

1 = normal (default).

DMSW

Digital microphone channel swap. Normal operation sends the left channel on the rising edge of the clock and

the right channel on the falling edge of the clock.

0 = normal (default).

1 = swap left and right channels.

INSEL

Digital microphone input select. When asserted, the on-chip ADCs are off, BCLK is master at 128 × fS, and

ADC_SDATA is expected to have left and right channels interleaved.

0 = digital microphone inputs off, ADCs enabled (default).

1 = digital microphone inputs enabled, ADCs off.

[1:0]

ADCEN[1:0]

ADC enable.

Setting

ADCs Enabled

Both off (default)

Left on

Right on

Both on

R20: Left Input Digital Volume, 16,410 (0x401A)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LADVOL[7:0]

Table 47. Left Input Digital Volume Register

Bits

Bit Name

Description

[7:0]

LADVOL[7:0]

Controls the digital volume attenuation for left channel inputs from either the left ADC or the left digital micro-

phone input. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 73 for a complete

list of the volume settings.

Setting

Volume Attenuation

00000000

0 dB (default)

00000001

−0.375 dB

00000010

−0.75 dB

…

11111110

−95.25 dB

11111111

−95.625 dB

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