ADAU1361BCPZ-R7 datasheet(47/80 Pages) AD

47 / 80 page

Data Sheet

ADAU1361

Rev. D | Page 47 of 80

Byte

Bits

Bit Name

Description

[6:3]

R[3:0]

PLL integer setting.

Setting

Value of R

0010

2 (default)

0011

0100

0101

0110

0111

1000

[2:1]

X[1:0]

PLL input clock divider.

Setting

Value of X

1 (default)

Type

Type of PLL. When set to integer mode, the values of M and N are ignored.

0 = integer (default).

1 = fractional.

Lock

PLL lock. This read-only bit is flagged when the PLL has finished locking.

0 = PLL unlocked (default).

1 = PLL locked.

PLLEN

PLL enable.

0 = PLL disabled (default).

1 = PLL enabled.

R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

JDDB[1:0]

JDFUNC[1:0]

Reserved

JDPOL

Table 29. Digital Microphone/Jack Detection Control Register

Bits

Bit Name

Description

[7:6]

JDDB[1:0]

Jack detect debounce time.

[5:4]

JDFUNC[1:0]

JACKDET/MICIN pin function. Enables or disables the jack detect function or configures the pin for a digital

microphone input.

JDPOL

Jack detect polarity. Detects high or low signal.

0 = detect high signal (default).

1 = detect low signal.

Setting

Debounce Time

5 ms (default)

10 ms

20 ms

40 ms

Setting

Pin Function

Jack detect off (default)

Jack detect on

Digital microphone input

Reserved

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