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SSM2519ACBZ-R7 数据表(PDF) 3 Page - Analog Devices

部件名 SSM2519ACBZ-R7
功能描述  Digital Input 2 W Class-D Audio Power Amplifier
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM2519ACBZ-R7 数据表(HTML) 3 Page - Analog Devices

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Data Sheet
SSM2519
Rev. 0 | Page 3 of 28
SPECIFICATIONS
All conditions at PVDD = 5.0 V; VDD = 1.8 V; fS = 48 kHz; MCLK = 128 × fS; TA = 25oC; RL = 8 Ω + 15 μH; default I2C settings; volume
control 0 dB setting, unless otherwise noted.
PERFORMANCE SPECIFICATIONS
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
DEVICE CHARACTERISTICS
Output Power
POUT
RL = 4 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0 V
2.31
W
RL = 4 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0 V
2.75
W
RL = 8 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0 V
1.35
W
RL = 8 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0 V
1.68
W
RL = 4 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6 V
1.13
W
RL = 4 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6 V
1.4
W
RL = 8 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6 V
0.69
W
RL = 8 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6 V
0.85
W
RL = 4 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5 V
0.48
W
RL = 4 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5 V
0.6
W
RL = 8 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5 V
0.31
W
RL = 8 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5 V
0.39
W
Efficiency
η
POUT = 2 W, 4 Ω, PVDD = 5.0 V
84
%
POUT = 1.4 W, 8 Ω, PVDD = 5.0 V, normal operation
90.2
%
Total Harmonic Distortion
Plus Noise
THD + N
POUT = 1 W into 8 Ω, f = 1 kHz, PVDD = 5.0 V
0.03
%
POUT = 0.5 W into 8 Ω, f = 1 kHz, PVDD = 3.6 V
0.03
%
Average Switching
Frequency
fSW
305
kHz
Differential Output Offset
VOOS
1
mV
Power Supply Rejection
Ratio
PSRRDC
PVDD = 2.5 V to 5.0 V
70
82
dB
PSRRGSM
VRIPPLE = 100 mV rms at 217 Hz, dither input
80
dB
Supply Current, PVDD
IPVDD
Dither input, 8 Ω + 15 μH load, PVDD = 5.0 V
2.64
mA
Dither input, 8 Ω + 15 μH load, PVDD = 3.6 V
2.24
mA
Dither input, 8 Ω + 15 μH load, PVDD = 2.5 V
2.02
mA
Dither input, 8 Ω + 15 μH load, PVDD = 3.6 V (DAC_LPM = 0 and
AMP_LPM = 0)
2.5
mA
Hardware shutdown
200
nA
Supply Current, VDD
IVDD
Dither input, VDD = 3.3 V
1.14
mA
Dither input, VDD = 1.8 V
0.6
mA
Software shutdown, clock present, VDD = 1.8 V
86
μA
Software shutdown, clock removed, VDD = 1.8 V
5
μA
Hardware shutdown
200
nA
Output Noise Voltage
en
PVDD = 5.0 V, f = 20 Hz to 20 kHz, dither input, A-weighted
37
μV
PVDD = 3.6 V, f = 20 Hz to 20 kHz, dither input, A-weighted, gain
= 3.6 V
41
μV
Signal-to-Noise Ratio
SNR
A-weighted reference to 0 dBFS, PVDD = 5.0 V
98
dB
Closed-Loop Gain
Gain
0 dBFS input, BTL output, f = 1 kHz
Gain = 5.0 V
4.94
V pk
Gain = 4.2 V
4.21
V pk
Gain = 3.6 V
3.69
V pk
Gain = 2 V
1.98
V pk



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