SSM2519

Data Sheet

Rev. 0 | Page 20 of 28

REGISTER DETAILS

SOFTWARE RESET AND MASTER SOFTWARE POWER-DOWN CONTROL REGISTER

Address: 0x00, Reset: 0x05, Name: PWR_CTRL

Table 16. Bit Descriptions for PWR_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

7

S_RST

Software reset. The software reset bit resets all internal blocks, including

0x0

RW

0

Normal operation

1

Software reset

6

RESERVED

Reserved.

0x0

RW

5

NO_BCLK

No BCLK operational mode. MCLK also used as BCLK.

0x0

RW

0

BCLK used as BCLK

1

MCLK used as BCLK. No signal needed on BCLK pin.

[4:1]

MCS

Master clock select. MCS must be set according to the input MCLK ratio

relative to the input sample frequency. Refer to Table 10.

0x2

RW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

Reserved

0

SPWDN

Master software power-down. Software power-down puts all blocks

0x1

RW

0

Normal operation

1

Software master power-down