Data Sheet

SSM2519

Rev. 0 | Page 21 of 28

EDGE SPEED, POWER, AND CLOCKING CONTROL REGISTER

Address: 0x01, Reset: 0x30, Name: SYS_CTRL

Table 17. Bit Descriptions for SYS_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

7

HPF_EN

DC blocking high-pass filter enable. The SSM2519 contains a selectable

high-pass filter. The −3 dB frequency is at 6 Hz with a 48 kHz sample rate.

This frequency increases linearly with lower sample rates.

0x0

RW

0

High-pass filter off

1

High-pass filter on

6

AMP_LPM

Amplifier low power mode.

0x0

RW

0

Normal operation

1

Low power (return to zero) Class-D mode

5

DAC_LPM

DAC low power mode.

0x1

RW

0

Normal operation

1

Low power operation mode. DAC runs at half speed.

4

APWDN_EN

Auto power-down enable. Auto power-down automatically puts the IC in

a low power state when 2048 consecutive zero input samples have been

received.

0x1

RW

0

Auto power-down disabled

1

Auto power-down enabled

[3:2]

EDGE

Edge rate control. This controls the edge speed of the power stage. The

low EMI operation mode reduces the edge speed, lowering EMI and

power efficiency.

0x0

RW

00

Normal operation

01

Lower EMI mode operation

10

Lower EMI mode operation

11

Lowest EMI mode operation

1

AMCS

Auto MCLK select.

0x0

RW

0

Master clock rate determined by MCS bits in Register 0x00

1

Master clock rate automatically detected

0

ASR

Autosample rate.

0x0

RW

0

Sample rate setting determined by FS bit in Register 0x02

1

Autosample and MCLK rate detection enabled