SSM2519ACBZ-R7 datasheet(12/28 Pages) AD

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SSM2519

Data Sheet

Rev. 0 | Page 12 of 28

THEORY OF OPERATION

OVERVIEW

The SSM2519 is a fully integrated digital switching audio

amplifier. The SSM2519 receives digital audio inputs and

produces the PDM differential switching outputs using an

internal power stage. The part has built-in protections against

overtemperature as well as overcurrent. The SSM2519 also has

built-in soft turn-on and soft turn-off for pop and click

suppression.

STANDALONE AND I2C OPERATIONAL MODE

The SSM2519 supports both standalone and I2C control modes.

The setting on the SD pin determines which mode is used.

Table 8. SD Pin Settings

SD Pin

Operation

Tie to VDD Through 20 kΩ

I2C

Connect to VDD Without 20 kΩ

Standalone mode

Connect to GND (Shorted or with 20 kΩ)

Shutdown mode

MASTER AND BIT CLOCK

The SSM2519 requires an external clock present at the MCLK

input pin to operate. This clock must be fully synchronous with

the incoming digital audio on the serial interface. Internal to the

IC, a clock frequency of 2.048 MHz to 24.576 MHz is required.

This internal clock is derived from the external MCLK by

dividing, passing through, or doubling in frequency the external

MCLK signal.

Different rates for MCLK are supported at different sample

rates. Refer to Table 9 for all available options. The MCLK rate

as well as sample rate can be automatically detected by setting

the AMCS and ASR bits in Register 0x01, or they can be manu-

ally set (MCS bits in Register 0x00, and FS bits in Register 0x02)

if AMCS or ASR is cleared.

When in standalone mode or in I2C mode and auto clock rate

detection is enabled (Register 0x01, Bit 1, AMCS = 1), the

internal clock generation circuitry is automatically configured.

When autosample rate detection is disabled (AMCS = 0), the

MCS bits in Register 0x00 must be set with the correct value to

generate the internal clock.

When the SSM2519 has entered its power-down state, it is

possible to gate this clock to conserve additional system power.

However, a master clock must be present for the audio amplifier

to operate.

If the serial interface bit clock (BCLK) is in the range of acceptable

internal master clock frequencies (between 2.048 MHz and

6.144 MHz), it can serve as both master clock and the bit clock.

Setting NO_BCLK (Bit 5 of Register 0x00) routes the signal on

the MCLK pin to serve as the internal bit clock as well. In this

case, tie the BCLK pin to ground.

Table 9. Supported MCLK Rate for Different Sample Frequencies

Sample Rates

Supported MCLK Rates

Supported MCLK Frequencies

8 kHz to 12 kHz

256 × fS/512 × fS/1024 × fS/1536 × fS/2048 × fS

2.048 MHz to 24.576 MHz

16 kHz to 24 kHz

128 × fS/256 × fS/512 × fS/768 × fS/1024 × fS

2.048 MHz to 24.576 MHz

32 kHz to 48 kHz

64 × fS/128 × fS/256 × fS/384 × fS/512 × fS

2.048 MHz to 24.576 MHz

8 kHz to 12 kHz

400 × fS/800 × fS/1600 × fS

3.2 MHz to 19.2 MHz

16 kHz to 24 kHz

200 × fS/400 × fS/800 × fS

3.2 MHz to 19.2 MHz

32 kHz to 48 kHz

100 × fS/200 × fS/400 × fS

3.2 MHz to 19.2 MHz

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