SSM2519ACBZ-R7 datasheet(14/28 Pages) AD

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SSM2519

Data Sheet

Rev. 0 | Page 14 of 28

POWER CONTROL

The IC starts up in software power-down mode, where all blocks

except for the I2C interface are disabled. To fully power up the

amplifier, clear SPWDN (Bit 0 of Register 0x00). In addition to

the software power-down, the software master mute control

(M_MUTE) is enabled at the initial state of the amplifier;

therefore, no audio is output until Bit 0 of Register 0x06 is

cleared.

The SSM2519 contains a smart power-down feature that, when

enabled, analyzes the incoming digital audio and, if the audio is

zero for 512 consecutive samples, regardless of sample rate,

places the IC in the smart power-down state. In this state, all

circuitry except the I2S ports are placed in a low power state.

After this state is entered, the I2S input and master clock

(MCLK) can be removed to place the part in its lowest power

state. When a single nonzero input is received, the SSM2519

leaves this state and resumes normal operation.

The SSM2519 can also be powered down to its lowest power

state by pulling the SD pin low.

POWER-ON RESET/VOLTAGE SUPERVISOR

The SSM2519 includes an internal power-on reset and voltage

supervisor circuit. This circuit provides an internal reset to all

circuitry during initial power-up. It also monitors the power

supplies to the IC, mutes the output, and issues a reset when the

voltages fall below the minimum operating range. This is done

to ensure that no damage occurs due to low voltage operation

and that no pops can occur under nearly any power removal

condition.

A soft reset of the chip can be issued through I2C by setting

Bit 7 of Register 0x00 (S_RST).

LOW POWER MODES

Two low power modes are available. If DAC_LPM (Bit 5 of

runs at half speed, reducing the quiescent current. This half

speed mode is also active when the MCS setting (Bits[4:1] of

the slowest acceptable MCLK rates can only support half speed

DAC operation.

If AMP_LPM (Bit 6 of Register 0x01) is set, the Σ-Δ modulator

runs in a special mode that offers lower quiescent current when

the output power is small, at the expense of slightly degraded

audio performance.

VOLUME CONTROL

The SSM2519 has a digital volume control. There are 255 levels

available, providing a range from +24 dB to −71.25 dB in

0.375 dB increments. This is a soft volume control, meaning

that the gain is adjusted continuously from one value to

another. This continuously adjusted gain prevents the audible

pop that occurs with an instantaneous gain adjustment.

ANALOG GAIN

The SSM2519 has selectable digital and analog gain. Selection

of these gains occurs via the GAIN pin. The analog gain settings

are optimized for operation at 2.5 V, 3.6 V, 4.2 V, or 5 V PVDD.

Table 13. GAIN Pin Configuration Control

GAIN Pin

Configuration

Analog Gain/Digital Gain

Tie to VDD

5 V optimized analog/0 dB digital gain

Tie to VDD

Through 150 kΩ

5 V optimized analog/6 dB digital gain

Tie to VDD

Through 47 kΩ

4.2 V optimized analog/0 dB digital gain

Tie to VDD

Through 15 kΩ

3.6 V optimized analog/−3 dB digital gain

Tie to GND

3.6 V optimized analog/0 dB digital gain

Table 14. Special Gain Case (LR_FORMAT Tied to VDD

Through 150 kΩ) GAIN Pin Configuration Control

GAIN Pin

Configuration

Analog Gain/Digital Gain

Tie to VDD

2.5 V optimized analog/−6.75 dB digital

gain

Tie to GND

3.6 V optimized analog/0 dB digital gain

FAULT DETECTION AND RECOVERY

Two fault conditions are detected by the SSM2519 fault

detection system: overcurrent and overtemperature. When

either of these is detected, the amplifier shuts down and a read-

only I2C bit is set to indicate the cause of the shutdown. The OC

and OT fault indicators are Bit 6 and Bit 5, respectively, of

temperature faults, current faults, or both, depending on the

state of ARCV (Bits[1:0] of Register 0x07).

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