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SSM2519ACBZ-R7 数据表(PDF) 4 Page - Analog Devices

部件名 SSM2519ACBZ-R7
功能描述  Digital Input 2 W Class-D Audio Power Amplifier
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM2519ACBZ-R7 数据表(HTML) 4 Page - Analog Devices

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SSM2519
Data Sheet
Rev. 0 | Page 4 of 28
POWER SUPPLY REQUIREMENTS
Table 2.
Parameter
Min
Typ
Max
Unit
PVDD
2.5
3.6
5.5
V
VDD
1.5
1.8
3.6
V
DIGITAL INPUT/OUTPUT
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT VOLTAGE
High (VIH)
0.7 × VDD
3.6
V
MCLK, BCLK, LRCLK, SDATA
1.35
5.5
V
SD, SDA, SCL
Low (VIL)
−0.3
+0.3 × VDD
V
MCLK, BCLK, LRCLK, SDATA
−0.3
+0.35
V
SD, SDA, SCL
INPUT LEAKAGE CURRENT
High (IIH)
1
μA
Excluding MCLK
Low (IIL)
1
μA
Excluding MCLK and bidirectional pin
MCLK INPUT LEAKAGE CURRENT
High (IIH)
3
μA
Low (IIL)
3
μA
INPUT CAPACITANCE
5
pF
DIGITAL TIMING
All timing specifications are given for the default setting (I2S mode) of the serial input port.
Table 4.
Limit
Parameter
Min
Max
Unit
Description
MASTER CLOCK
tMP
74
136
ns
MCLK period, 256 × fS mode (MCS = b0010)
tMP
148
271
ns
MCLK period, 128 × fS mode (MCS = b0001)
SERIAL PORT
tBIL
40
ns
BCLK low pulse width
tBIH
40
ns
BCLK high pulse width
tLIS
10
ns
Setup time from LRCLK or SDATA edge to BCLK rising edge
tLIH
10
ns
Hold time from BCLK rising edge to LRCLK or SDATA edge
tSIS
10
ns
SDATA setup time to BCLK rising
tSIH
10
ns
SDATA hold time from BCLK rising
I2C PORT
fSCL
400
kHz
SCL frequency
tSCLH
0.6
μs
SCL high
tSCLL
1.3
μs
SCL low
tSCS
0.6
μs
Setup time; relevant for repeated start condition
tSCH
0.6
μs
Hold time; after this period, the first clock is generated
tDS
100
ns
Data setup time
tSCR
300
ns
SCL rise time
tSCF
300
ns
SCL fall time
tSDR
300
ns
SDA rise time
tSDF
300
ns
SDA fall time
tBFT
0.6
μs
Bus-free time (time between stop and start)



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