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SSM2519ACBZ-R7 数据表(PDF) 13 Page - Analog Devices |
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SSM2519ACBZ-R7 数据表(HTML) 13 Page - Analog Devices |
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13 / 28 page  Data Sheet SSM2519 Rev. 0 | Page 13 of 28 Table 10. Master Clock Select (MCS) Bit Settings: MCLK, Ratio, and Frequency Input Sample Rate Ratio/ MCLK Setting 0, b0000 Setting 1, b0001 Setting 2, b0010 Setting 3, b0011 Setting 4, b0100 Setting 5, b0101 Setting 6, b0110 Setting 7, b0111 Setting 8, b1000 8 kHz Ratio 256 × fS1 512 × fS 1024 × fS 1536 × fS 2048 × fS 3072 × fS 400 × fS 800 × fS 1600 × fS MCLK 2.048 MHz 4.096 MHz 8.192 MHz 12.288 MHz 16.384 MHz 24.576 MHz 3.20 MHz 6.40 MHz 12.80 MHz 11.025 kHz Ratio 256 × fS1 512 × fS 1024 × fS 1536 × fS 2048 × fS 3072 × fS 400 × fS 800 × fS 1600 × fS MCLK 2.822 MHz 5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz 33.8688 MHz 4.41 MHz 8.82 MHz 17.64 MHz 12 kHz Ratio 256 × fS1 512 × fS 1024 × fS 1536 × fS 2048 × fS 3072 × fS 400 × fS 800 × fS 1600 × fS MCLK 3.072 MHz 6.144 MHz 12.288 MHz 18.432 MHz 24.576 MHz 38.864 MHz 4.80 MHz 9.60 MHz 19.20 MHz 16 kHz Ratio 128 × fS1 256 × fS 384 × fS 768 × fS 1024 × fS 1536 × fS 200 × fS 400 × fS 800 × fS MCLK 2.048 MHz 4.096 MHz 8.192 MHz 12.288 MHz 16.384 MHz 24.576 MHz 3.20 MHz 6.40 MHz 12.80 MHz 22.05 kHz Ratio 128 × fS1 256 × fS 512 × fS 768 × fS 1024 × fS 1536 × fS 200 × fS 400 × fS 800 × fS MCLK 2.822 MHz 5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz 33.8688 MHz 4.41 MHz 8.82 MHz 17.64 MHz 24 kHz Ratio 128 × fS1 256 × fS 512 × fS 768 × fS 1024 × fS 1536 × fS 200 × fS 400 × fS 800 × fS MCLK 3.072 MHz 6.144 MHz 12.288 MHz 18.432 MHz 24.576 MHz 38.864 MHz 4.80 MHz 9.60 MHz 19.20 MHz 32 kHz Ratio 64 × fS1 128 × fS 256 × fS 384 × fS 512 × fS 768 × fS 100 × fS 200 × fS 400 × fS MCLK 2.048 MHz 4.096 MHz 8.192 MHz 12.288 MHz 16.384 MHz 24.576 MHz 3.20 MHz 6.40 MHz 12.80 MHz 44.1 kHz Ratio 64 × fS1 128 × fS 256 × fS 384 × fS 512 × fS 768 × fS 100 × fS 200 × fS 400 × fS MCLK 2.822 MHz 5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz 33.8688 MHz 4.41 MHz 8.82 MHz 17.64 MHz 48 kHz Ratio 64 × fS1 128 × fS 256 × fS 384 × fS 512 × fS 768 × fS 100 × fS 200 × fS 400 × fS MCLK 3.072 MHz 6.144 MHz 12.288 MHz 18.432 MHz 24.576 MHz 38.864 MHz 4.80 MHz 9.60 MHz 19.20 MHz 1 When using MCS = 0/64 fS mode, the chip automatically operates in low power mode. DIGITAL INPUT SERIAL AUDIO INTERFACE It is capable of receiving stereo I2S, left justified, or right justified data. Mono, stereo, and multichannel PCM/TDM interface formats are available. The data and interface formats are selected by adjusting the SDATA_FMT and SAI bits in Register 0x02. Note that, when operating in right justified mode, the proper data width must be chosen. The BCLK signal does not have to be provided to the SSM2519. It can internally generate the appropriate BCLK signal. To operate without a BCLK, the BCLK pin should be tied to VDD or GND to select the appropriate BCLK rate for the SDATA input. Table 11. BCLK Pin Connection Options BCLK Pin Generation BCLK Rate Connected to External Clock Source External Any Tied to VDD Internal 16 bit clocks/channel Tied to GND Internal 32 bit clocks/channel When the SSM2519 is set up in standalone mode, a subset of serial interface formats are available. Selection of these serial formats and input channel are determined by the LR_FORMAT pin. Table 12. LR_FORMAT Pin Configuration Controls LR_FORMAT Pin Configuration Serial Format/Channel Select Tie to VDD I2S/left channel Tie to VDD Through 150 kΩ Special gain case1 (I2S/left channel) Tie to VDD Through 47 kΩ PCM/left channel Tie to VDD Through 15 kΩ LJ/left channel Tie to GND I2S/right channel 1 See Table 14. CHANNEL MAPPING Stereo audio formats and TDM formats with two, four, eight, or 16 channels are available. In these modes, the amplifier audio can be chosen from any of the available TDM slots using the CH_SEL bits in Register 0x04. For most digital interface formats, many of these options are not present. For example, in stereo modes, only Channel 0 and Channel 1 are valid, and in four-slot TDM mode, only Channel 0, Channel 1, Channel 2, and Channel 3 are valid. POWER SUPPLIES The SSM2519 has two internal power supplies that must be provided. PVDD supplies power to the full-bridge power stage of MOSFETs and its associated drive, control, and protection circuitry. PVDD can operate from 2.5 V to 5.5 V and must be present to obtain audio output. Lowering the PVDD supply results in lower output power and correspondingly lower power consumption. This does not affect audio performance. VDD provides power to the digital logic, analog components, and I/O circuitry. VDD can operate from 1.5 V to 3.6 V and must be provided to obtain audio output. Lowering the supply voltage results in lower power consumption, but does not result in lower audio performance. |
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