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CS42406 数据表(PDF) 21 Page - Cirrus Logic

部件名 CS42406
功能描述  24-BIT, 192kHz 2-IN 6-OUT AUDIO CODEC
PDF  50 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS42406 数据表(HTML) 21 Page - Cirrus Logic

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CS42406
21
SWITCHING CHARACTERISTICS - DAC SERIAL AUDIO PORT (Logic “0” = GND =
0 V, Logic “1” = VLS)
* For a description of Speed Modes, please refer to Section 4.1.2 on page 30.
Parameter
Symbol
Min
Typ
Max
Unit
MCLK Specifications
MCLK Frequency
1.024
-
12.8
MHz
22
-
25.6
MHz
MCLK Duty Cycle
45
-
55
%
Single-Speed*
DAC_LRCK Duty Cycle
45
-
55
%
DAC_SCLK Frequency
-
-
128
×Fs
Hz
DAC_SCLK Pulse Width Low
tsclkl
20
-
-
ns
DAC_SCLK Pulse Width High
tsclkh
20
-
-
ns
DAC_SCLK rising to DAC_LRCK edge delay
tslrd
20
ns
DAC_SCLK rising to DAC_LRCK edge setup time
tslrs
20
ns
SDINx valid to DAC_SCLK rising setup time
tsdlrs
20
ns
DAC_SCLK rising to SDINx hold time
tsdh
20
ns
Double-Speed*
DAC_LRCK Duty Cycle
45
-
55
%
DAC_SCLK Frequency
-
-
64
×Fs
Hz
DAC_SCLK Pulse Width Low
tsclkl
20
-
-
ns
DAC_SCLK Pulse Width High
tsclkh
20
-
-
ns
DAC_SCLK rising to DAC_LRCK edge delay
tslrd
20
ns
DAC_SCLK rising to DAC_LRCK edge setup time
tslrs
20
ns
SDINx valid to DAC_SCLK rising setup time
tsdlrs
20
ns
DAC_SCLK rising to SDINx hold time
tsdh
20
ns
Quad-Speed*
DAC_LRCK Duty Cycle
45
-
55
%
DAC_SCLK Frequency
-
-
MCLK/2
Hz
DAC_SCLK Pulse Width Low
tsclkl
20
-
-
ns
DAC_SCLK Pulse Width High
tsclkh
20
-
-
ns
DAC_SCLK rising to DAC_LRCK edge delay
tslrd
20
ns
DAC_SCLK rising to DAC_LRCK edge setup time
tslrs
20
ns
SDINx valid to DAC_SCLK rising setup time
tsdlrs
20
ns
DAC_SCLK rising to SDINx hold time
tsdh
20
ns



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