CS42406 datasheet(24/50 Pages) CIRRUS

24 / 50 page

CS42406

DS614PP5

* For a description of Speed Modes, please refer to Table 1 on page 30.

18. Internal ÷ is automatically determined when operating within the specified limits.

256x Mode

(pin 6 = LO)

MCLK Frequency (Note 18)

Internal ÷1

1.024

12.8

MHz

Internal ÷2

22.016

25.6

MHz

Master Mode

ADC_SCLK Duty Cycle

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

ADC_LRCK Frequency (Note 18)

MCLK = 64 Fs (÷1)

Quad-Speed Mode

100

200

kHz

Slave Mode

ADC_SCLK Period

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

tsclkw

156

ADC_SCLK Duty Cycle

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

384x Mode

(pin 6 = HI)

MCLK Frequency (Note 18)

Internal ÷1.5

1.536

19.2

MHz

Internal ÷3

33.024

38.4

MHz

Master Mode

ADC_SCLK Duty Cycle

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

ADC_LRCK Frequency (Note 18)

MCLK = 96 Fs (÷1.5)

Quad-Speed Mode

100

200

kHz

Slave Mode

ADC_SCLK Period

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

tsclkw

290

193

104

ADC_SCLK Duty Cycle

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

CS42406 数据表(PDF) 24 Page - Cirrus Logic

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CS42406 数据表(PDF) 24 Page - Cirrus Logic

CS42406 数据表(HTML) 24 Page - Cirrus Logic

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