CS42406 datasheet(34/50 Pages) CIRRUS

34 / 50 page

CS42406

DS614PP5

4.5

Analog Connections

The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stop-

band of the filter. However, there is no rejection for input signals which are multiples of the input sampling

frequency (n

* 6.144 MHz), where n=0, 1, 2, ... Refer to Figure 36 which shows the suggested filter that

will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for

the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose

ceramics) must be avoided since these can degrade signal linearity.

4.5.1

Capacitor Size on the Reference Pin (FILT+)

The CS42406 requires an external capacitance on the internal reference voltage pin, ADC_FILT+. The

size of this decoupling capacitor will affect the low frequency distortion performance as shown in Figure

37, with larger capacitor values used to optimize low frequency distortion performance.

*Place as close to

the CS42406 as

possi bl e.

4.7

µF

100 k

Ω

100 k

Ω

470 pF

C0G

634

Ω

2200 pF

C0G

AINL

AINR

CS42406

Input1

4.7

µF

100 k

Ω

100 k

Ω

470 pF

C0G

634

Ω

2200 pF

C0G

Input2

Figure 36. CS42406 Recommended Analog Input Buffer

47 uF

100 uF

22 uF

10 uF

6.8 uF

4.7 uF

3.3 uF

2.2 uF

1 uF

5.6 uF

Figure 37. CS42406 ADC: THD+N versus Frequency

CS42406 数据表(PDF) 34 Page - Cirrus Logic

CS42406 数据表(HTML) 34 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

数据表下载

链接网址

CS42406 数据表(PDF) 34 Page - Cirrus Logic

CS42406 数据表(HTML) 34 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

数据表 下载

链接网址

数据表下载