STSPIN32F0ATR datasheet(21/41 Pages) STMICROELECTRONICS

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STSPIN32F0A

Device description

DocID030766 Rev 2.0

21/41

Device description

The STSPIN32F0A is a System-In-Package providing an integrated solution suitable for

driving the three-phase BLDC motors. The device will be developed in the BCD8s (0.18

µm) technology.

6.1

UVLO and thermal protections

Table 9: "UVLO and OT protection management" summarizes the UVLO and OT protection

management.

Table 9: UVLO and OT protection management

Block

VM UVLO

VDD

UVLO

VREG12

UVLO

VBOOT

UVLO

Lin. Reg

DC/DC Reg

DC/DC regulator

OFF

Linear regulator

OFF

Op amps and OC comp

OFF

HSU, HSV, HSW output

LOW

LOW (1)

LOW(1), (2)

LSU, LSV, LSW output

LOW

LOW(1)

Notes:

(1)The N-channel of the gate driver is turned ON with all the available supply voltage, refer to Figure 5: "Gate drivers' outputs

characteristics in UVLO conditions".

(2)Only the high-side gate driver in which the UVLO condition is detected (e.g. UVLO on VBOOTU causes the HSU turning off).

Figure 5: Gate drivers' outputs characteristics in UVLO conditions

100

150

200

250

300

350

400

450

500

550

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

VLVG/HVG (V)

Vcc = 1 V

Vcc = 2 V

Vcc = 3 V

Vcc = 4 V

Vcc = VREG for LS rails

Vcc = VBOOT -VOUT for HS rails

Vcc = 0 V

ILVG/HVG

(mA)

Vcc = 6 to 12 V

Vcc = 5 V

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