List of figures

STSPIN32F0A

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DocID030766 Rev 2.0

List of figures

Figure 1: STSPIN32F0A System-In-Package block diagram .....................................................................6

Figure 2: Analog IC block diagram .............................................................................................................7

Figure 3: Gate drivers timing ....................................................................................................................14

Figure 4: STSPIN32F0A SiP pin connection (top view) ...........................................................................15

Figure 5: Gate drivers' outputs characteristics in UVLO conditions .........................................................21

Figure 6: Power-up and power-down sequence .......................................................................................22

Figure 7: DC/DC buck regulator topology.................................................................................................23

Figure 8: Soft-start timing .........................................................................................................................23

Figure 9: Linear regulator block diagram ..................................................................................................24

Figure 10: Linear regulator output characteristics ....................................................................................25

Figure 11: “Standby to normal” operation timing (CREG = 1 µF) .............................................................26

Figure 12: HSE clock source timing diagram ...........................................................................................29

Figure 13: Typical application with 8 MHz crystal.....................................................................................29

Figure 14: Operational amplifiers..............................................................................................................30

Figure 15: Comparator..............................................................................................................................31

Figure 16: Driver logic overcurrent management signals .........................................................................32

Figure 17: ESD protection strategy...........................................................................................................33

Figure 18: Application example ................................................................................................................35

Figure 19: VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 package outline .........................................................37

Figure 20: VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 - suggested footprint .................................................38