STSPIN32F0ATR datasheet(28/41 Pages) STMICROELECTRONICS

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Device description

STSPIN32F0A

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DocID030766 Rev 2.0

The VDDA voltage level must be always greater or equal to the VDD voltage

level and must be established first.

The MCU has integrated power-on reset (POR) and power-down reset (PDR) circuits. They

are always active, and ensure proper operation above a threshold of 2 V. The device

remains in the reset mode when the monitored supply voltage is below a specified

threshold.

•

The POR monitors only the VDD supply voltage. During the startup phase it is required

that VDDA should arrive first and be greater than or equal to VDD.

•

The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power

supply supervisor can be disabled (by programming a dedicated option bit) to reduce

the power consumption if the application design ensures that VDDA is higher than or

equal to VDD.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD power supply and compares it to the VPVD threshold. An interrupt can be generated

when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD

threshold. The interrupt service routine can then generate a warning message and/or put

the MCU into a safe state. The PVD is enabled by software.

The MCU supports three low-power modes to achieve the best compromise between low-

power consumption, short start-up time and available wake-up sources:

•

Sleep mode

•

In the sleep mode, only the CPU is stopped. All peripherals continue to operate and

can wake-up the CPU when an interrupt/event occurs.

•

Stop mode

•

The stop mode achieves very low-power consumption while retaining the content of

the SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI

RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in the normal or in the low-power mode.

•

The device can be woken-up from the stop mode by any of the EXTI lines (one of the

16 external lines, the PVD output, RTC, I2C1 or USART1).

•

Standby mode

•

The standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

the standby mode, SRAM and register contents are lost except for registers in the

RTC domain and standby circuitry.

•

The device exits the standby mode when an external reset (NRST pin), an IWDG

reset,

•

a rising edge on the WKUP pins, or an RTC event occurs.

6.6.3

High-speed external clock source

The high-speed external (HSE) clock can be generated from the external clock signal or

supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator (see Figure 13: "Typical

application with 8 MHz crystal").

The external clock signal has to respect the I/O characteristics and follows the

recommended clock input waveform (refer to Figure 12: "HSE clock source timing

diagram").

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