| 数据搜索系统,热门电子元器件搜索 |
|
STSPIN32F0ATR 数据表(PDF) 24 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STSPIN32F0ATR 数据表(HTML) 24 Page - STMicroelectronics |
|
24 / 41 page ![]() Device description STSPIN32F0A 24/41 DocID030766 Rev 2.0 It is not allowed to apply VDD voltage externally in case of VM < VDD. 6.3 Linear regulator The internal 12 V linear regulator is a LDO regulator providing the supply voltage for the gate drivers section. An external capacitor connected to the VREG12 pin is required. Figure 9: Linear regulator block diagram When the VM voltage is below to 12 V, the VM pin and the linear regulator output can be shorted together providing the gate driver supply externally. The linear regulator embeds a thermal protection as described in Section 6.1.2: "Thermal protection". 12 V LIN regulator VM VREG12 C REG VREG12 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |