PCF8564A datasheet(33/65 Pages) NXP

33 / 65 page

PCF85063A

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Product data sheet

Rev. 7 — 30 March 2018

33 of 65

NXP Semiconductors

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

Characteristics of the I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse, as changes in the data line at this time

are interpreted as a control signal (see Figure 18).

9.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 19).

9.3 System configuration

A device generating a message is a transmitter; a device receiving a message is a

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves (see Figure 20).

Fig 18. Bit transfer

Fig 19. Definition of START and STOP conditions

PCF8564A 数据表(PDF) 33 Page - NXP Semiconductors