PCF8564A datasheet(12/65 Pages) NXP

12 / 65 page

PCF85063A

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Product data sheet

Rev. 7 — 30 March 2018

12 of 65

NXP Semiconductors

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

8.2.1.3

Software reset

A reset is automatically generated at power-on. There is a low probability that some

devices will have corruption of the registers after the automatic power-on reset if the

device is powered up with a residual VDD level. It is required that the VDD starts at zero

volts at power up or upon power cycling to ensure that there is no corruption of the

registers. If this is not possible, a reset must be initiated after power-up (i.e. when power is

stable) with the software reset command. Software reset command means setting bits 6,

4, and 3 in register Control_1 (00h) logic 1 and all other bits logic 0 by sending the bit

sequence 01011000 (58h), see Figure 8.

In reset state, all registers are set according to Table 8 and the address pointer returns to

address 00h.

After sending the software reset command, it is recommended to re-initialize the interface by a STOP and START.

Fig 8.

Software reset command

Table 8.

Registers reset values

Address

Bit

00h

Control_1

00000000

01h

Control_2

00000000

02h

Offset

00000000

03h

RAM_byte

00000000

04h

Seconds

10000000

05h

Minutes

00000000

06h

Hours

00000000

07h

Days

00000001

08h

Weekdays

00000110

09h

Months

00000001

0Ah

Years

00000000

0Bh

Second_alarm

10000000

0Ch

Minute_alarm

10000000

0Dh

Hour_alarm

10000000

0Eh

Day_alarm

10000000

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