PCF8564A datasheet(36/65 Pages) NXP

36 / 65 page

PCF85063A

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Product data sheet

Rev. 7 — 30 March 2018

36 of 65

NXP Semiconductors

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

9.5.2.1

I2C-bus error recovery technique

Slave devices like the PCF85063A use a state machine to implement the I2C protocol and

expect a certain sequence of events to occur to function properly. Unexpected events at

the I2C master can wreak havoc with the slaves connected on the bus. However, it is

usually possible to recover deterministically to a known bus state with careful protocol

manipulation.

A deterministic method to clear this situation if SDA is stuck LOW (it effectively blocks any

other I2C-bus transaction, once the master recognizes a ‘stuck bus’ state), is for the

master to blindly transmit nine clocks on SCL. If the slave was transmitting data or

acknowledging, nine or more clocks ensures the slave state machine returns to a known,

idle state since the protocol calls for eight data bits and one ACK bit. It does not matter

when the slave state machine finishes its transmission; extra clocks are recognized as

STOP conditions.

With careful design of the bus master error recovery firmware, many I2C-bus protocol

problems can be avoided.

S/W considerations: NXP recommends customers allow for S/W reset capability to enable

the bus error recovery technique. The 9-clock pulse method as described above involves

a bus-master capable of providing such a signal.

Further comments/additional information are available in Ref. 17 “UM10301” and Ref. 16

“UM10204”.

For multimaster configurations and to fasten the communication, the STOP-START sequence can be replaced by a repeated

START (Sr).

Fig 23. Master reads after setting register address (write register address; READ data)

PCF8564A 数据表(PDF) 36 Page - NXP Semiconductors