PCF8564A datasheet(64/65 Pages) NXP

64 / 65 page

PCF85063A

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Product data sheet

Rev. 7 — 30 March 2018

64 of 65

NXP Semiconductors

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

27. Figures

Fig 1.

Block diagram of PCF85063A . . . . . . . . . . . . . . . .3

Fig 2.

Pin configuration for SO8 (PCF85063AT) . . . . . . .4

Fig 3.

Pin configuration for DFN2626-10

(PCF85063ATL) . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 4.

Pin configuration for TSSOP8 (PCF85063ATT). . .4

Fig 5.

Handling address registers . . . . . . . . . . . . . . . . . .6

Fig 6.

STOP bit functional diagram . . . . . . . . . . . . . . . .10

Fig 7.

STOP bit release timing . . . . . . . . . . . . . . . . . . . . 11

Fig 8.

Software reset command . . . . . . . . . . . . . . . . . . .12

Fig 9.

Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 10. INT example for MI . . . . . . . . . . . . . . . . . . . . . . .15

Fig 11. Offset calibration calculation workflow . . . . . . . . .20

Fig 12. Result of offset calibration . . . . . . . . . . . . . . . . . .21

Fig 13. OS flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 14. Data flow for the time function . . . . . . . . . . . . . . .25

Fig 15. Access time for read/write operations . . . . . . . . .26

Fig 16. Alarm function block diagram. . . . . . . . . . . . . . . .29

Fig 17. General countdown timer behavior . . . . . . . . . . .31

Fig 18. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Fig 19. Definition of START and STOP conditions. . . . . .33

Fig 20. System configuration . . . . . . . . . . . . . . . . . . . . . .34

Fig 21. Acknowledgement on the I2C-bus . . . . . . . . . . . .34

Fig 22. Master transmits to slave receiver

(WRITE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Fig 23. Master reads after setting register address

(write register address; READ data) . . . . . . . . . .36

Fig 24. Device diode protection diagram of PCF85063A.37

Fig 25. Typical IDD with respect to fSCL . . . . . . . . . . . . . .40

Fig 26. Typical IDD as a function of temperature . . . . . . .41

Fig 27. Typical IDD with respect to VDD . . . . . . . . . . . . . .42

Fig 28. IDD with respect to quartz RS . . . . . . . . . . . . . . . .43

Fig 29. Oscillator frequency variation with respect

to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Fig 30. I2C-bus timing diagram; rise and fall times

refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . .45

Fig 31. Application diagram for PCF85063A . . . . . . . . . .46

Fig 32. Package outline SOT96-1 (SO8) of

PCF85063AT . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Fig 33. Package outline SOT1197-1 (DFN2626-10) of

PCF85063ATL . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Fig 34. Package outline SOT505-1 (TSSOP8) of

PCF85063ATT . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Fig 35. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Fig 36. Footprint information for reflow soldering of

SOT96-1 (SO8) of PCF85063AT . . . . . . . . . . . . .53

Fig 37. Footprint information for reflow soldering of

SOT1197-1 (DFN2626-10) of PCF85063ATL . . .54

Fig 38. Footprint information for reflow soldering of

SOT505-1 (TSSOP8) of PCF85063ATT . . . . . . .55

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