PCF8564A datasheet(34/65 Pages) NXP

34 / 65 page

PCF85063A

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Product data sheet

Rev. 7 — 30 March 2018

34 of 65

NXP Semiconductors

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

9.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered)

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition

Acknowledgement on the I2C-bus is shown in Figure 21.

Fig 20. System configuration

Fig 21. Acknowledgement on the I2C-bus

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