PCF8564A datasheet(35/65 Pages) NXP

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PCF85063A

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Product data sheet

Rev. 7 — 30 March 2018

35 of 65

NXP Semiconductors

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

9.5 I2C-bus protocol

9.5.1 Addressing

One I2C-bus slave address (1010001) is reserved for the PCF85063A. The entire I2C-bus

slave address byte is shown in Table 39.

After a START condition, the I2C slave address has to be sent to the PCF85063A device.

The R/W bit defines the direction of the following single or multiple byte data transfer

(R/W = 0 for writing, R/W = 1 for reading). For the format and the timing of the START

condition (S), the STOP condition (P) and the acknowledge bit (A) refer to the I2C-bus

characteristics (see Ref. 16 “UM10204”). In the write mode, a data transfer is terminated

by sending either the STOP condition or the START condition of the next data transfer.

9.5.2 Clock and calendar READ or WRITE cycles

The I2C-bus configuration for the different PCF85063A READ and WRITE cycles is shown

in Figure 22 and Figure 23. The register address is a 5-bit value that defines which

Table 39.

I2C slave address byte

Slave address

Bit

MSB

LSB

1R/W

Fig 22. Master transmits to slave receiver (WRITE mode)

PCF8564A 数据表(PDF) 35 Page - NXP Semiconductors