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ST7LITE3 数据表(PDF) 102 Page - STMicroelectronics |
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ST7LITE3 数据表(HTML) 102 Page - STMicroelectronics |
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102 / 167 page ![]() ST7LITE3 102/167 LINSCI ™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 = ERPR[7:0] 8-bit Extended Receive Pres- caler Register. The extended Baud Rate Generator is activated when a value other than 00h is stored in this regis- ter. The clock frequency from the 16 divider (see Figure 56) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended baud rate generator is not active af- ter a reset. EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (SCIETPR) Read/Write Reset Value:0000 0000 (00h) Bit 7:0 = ETPR[7:0] 8-bit Extended Transmit Pres- caler Register. The extended Baud Rate Generator is activated when a value other than 00h is stored in this regis- ter. The clock frequency from the 16 divider (see Figure 56) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended baud rate generator is not active af- ter a reset. Note: In LIN slave mode, the Conventional and Extended Baud Rate Generators are disabled. 7 0 ERPR 7 ERPR 6 ERPR 5 ERPR 4 ERPR 3 ERPR 2 ERPR 1 ERPR 0 7 0 ETPR 7 ETPR 6 ETPR 5 ETPR 4 ETPR 3 ETPR 2 ETPR 1 ETPR 0 |
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