ST7LITE3 datasheet(103/167 Pages) STMICROELECTRONICS

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ST7LITE3

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LINSCI

™ SERIAL COMMUNICATION INTERFACE (LIN Mode)

11.5.9 LIN Mode - Functional Description.

The block diagram of the Serial Control Interface,

in LIN slave mode is shown in Figure 58.

It uses 6 registers:

– Three control registers: SCICR1, SCICR2 and

SCICR3

– Two status registers: the SCISR register and the

LHLR register mapped at the SCIERPR address

– A baud rate register: LPR mapped at the SCI-

BRR address and an associated fraction register

LPFR mapped at the SCIETPR address

The bits dedicated to LIN are located in the

SCICR3. Refer to the register descriptions in Sec-

tion 11.5.10for the definitions of each bit.

11.5.9.1 Entering LIN Mode

To use the LINSCI in LIN mode the following con-

figuration must be set in SCICR3 register:

– Clear the M bit to configure 8-bit word length.

– Set the LINE bit.

Master

To enter master mode the LSLV bit must be reset

In this case, setting the SBK bit will send 13 low

bits.

Then the baud rate can programmed using the

SCIBRR, SCIERPR and SCIETPR registers.

In LIN master mode, the Conventional and / or Ex-

tended Prescaler define the baud rate (as in stand-

ard SCI mode)

Slave

Set the LSLV bit in the SCICR3 register to enter

LIN slave mode. In this case, setting the SBK bit

will have no effect.

In LIN Slave mode the LIN baud rate generator is

selected instead of the Conventional or Extended

Prescaler. The LIN baud rate generator is com-

mon to the transmitter and the receiver.

Then the baud rate can be programmed using

LPR and LPRF registers.

Note: It is mandatory to set the LIN configuration

first before programming LPR and LPRF, because

the LIN configuration uses a different baud rate

generator from the standard one.

11.5.9.2 LIN Transmission

In LIN mode the same procedure as in SCI mode

has to be applied for a LIN transmission.

To transmit the LIN Header the proceed as fol-

lows:

– First set the SBK bit in the SCICR2 register to

start transmitting a 13-bit LIN Synch Break

– reset the SBK bit

– Load the LIN Synch Field (0x55) in the SCIDR

– Wait until the SCIDR is empty (TDRE bit set in

the SCISR register)

– Load the LIN message Identifier in the SCIDR

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