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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITE3 数据表(PDF) 105 Page - STMicroelectronics |
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ST7LITE3 数据表(HTML) 105 Page - STMicroelectronics |
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105 / 167 page  ST7LITE3 105/167 LINSCI ™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d) Figure 58. SCI Block Diagram in LIN Slave Mode WAKE UP UNIT RECEIVER CONTROL SCISR TRANSMIT CONTROL TDRE TC RDRF IDLE OR/ NF FE PE SCI CONTROL INTERRUPT SCICR1 R8 T8 SCID M WAKE PCE PS PIE Received Data Register (RDR) Receive Shift Register Read Transmit Data Register (TDR) Transmit Shift Register Write RDI TDO (DATA REGISTER) SCIDR TRANSMITTER CLOCK RECEIVER CLOCK fCPU / LDIV SBK RWU RE TE ILIE RIE TCIE TIE SCICR2 LIN SLAVE BAUD RATE AUTO SYNCHRONIZATION fCPU SCICR3 LINE LASE LHIE LSF LHDF EXTENDED PRESCALER CONVENTIONAL BAUD RATE GENERATOR + /16 SCIBRR LPR7 LPR0 LIN SLAVE BAUD RATE GENERATOR 0 1 UNIT LDUM LHDM LHE LSLV |
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