7.11

Pulse skip

At light loads, the device works in discontinuous conduction mode. Zero-cross comparator is implemented to

the DCM operations both power MOSFETs are off and the efficiency is improved according to that. Moreover, the

sleep period is a function of the load.

the proper regulation to light load (or no load conditions).

In addition, the pulse skip threshold (i.e. the voltage the device enters the pulse skip operation) can be properly

selected to optimize the efficiency at light loads.

7.12

Bus timing

As shown in the figure below, the data on the SDA line must be stable during the high semi-period of the clock.

The high and low-state of the data line can only change when the clock signal on the SCL line is low.

SDA

SCL

Data line stable

Data valid

Data change

allowed

Each bus transaction begins with a “START” command which is defined as SDA transition from 1 to 0 with SCL

high, and it is finished with a “STOP” command, which is defined as SDA transition from 0 to 1 with SCL high, as

shown in Figure 38. START and STOP commands.

Stop

Condition

Start

Condition

SDA

SCL

The master generates the start command and transmits the 7-bit address and the read/write bit on SDA line. All

slave devices compare the address sent by the master to their internal fixed addresses. Only the slave device,

SCL clock. The acknowledge bit is used to indicate a successful byte transfer.

STPD01

Pulse skip

DS13473 - Rev 1

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