Connect all the ground metallization and/or layers with as many vias as possible. The vias should be located at

minimum keepout distance; this should be done to minimize resistive and inductive parasitic effects.

Reference voltage

Vreg is generated by an internal LDO. Place a decoupling capacitor very close. Use good capacitor layout

techniques. Do not route the Vref trace near noisy traces or planes.

High-side driver supply

VDRIVEH is generated by an internal LDO. Place a decoupling capacitor very close. Use good capacitor layout

techniques. Do not route the Vref trace near noisy traces or planes.

Current sensing

With small value sense resistors, trace resistance shared with the load can cause significant errors. It is

recommended to connect the sense resistor pads directly to the ISNS+ and ISNS- pins using “Kelvin” or “4-wire”

connection techniques as shown in Figure 43. RSNS Kelvin connection (sx sense in the same layer, at dx with

vias top to bottom). Run two dedicated traces with decent width in parallel (close to each other to minimize the

loop area) from the two terminals of the current-sensing resistor to the IC. Place in the differential mode and avoid

sense lines pass through noisy areas, such as switch nodes.

The ISNS+ and ISNS- pins tolerate a DC voltage of -0.3 V with respect to GND. If VISNS+ and VISNS- pins are

forecasted to go below the DC value for short AC pulses, the source current must be limited to a max. of 10 mA.

Thermal aspects

The STPD01 power dissipation inside the IC is mainly due to the DC-DC integrated MOSFET power loss. The

heat generated due to this power dissipation level requires a suitable heatsink to keep the junction temperature

below the overtemperature protection threshold at the rated ambient temperature. Try, where possible, to increase

the number of power planes connected, at least below the IC position, to improve the heat dissipation. However,

different layouts are also possible. Basic principles suggest keeping the IC and its ground exposed pad

approximately in the middle of the dissipating area; to provide as many vias as possible; to design a dissipating

area having a shape as square as possible and not interrupted by other copper traces.

STPD01

Board layout guidelines

DS13473 - Rev 1

page 32/43