The master then generates further SCL cycles to either transmit data to the slave or receive data from the slave.

At the end of the data transfer, the master generates the stop command and the bus is released and all devices

wait for a new start command.

7.12.1

Read and write commands

consists of eight bits with most significant bit first and least significant bit last.

Write command to the transceiver device is described by the following figure. It is possible to write to several

consecutive registers during one write command.

Slave Address

S

R/W

A

A

A

P

Register Address

Data

7 bits

1

1

1

1

1

1

8 bits

8 bits

“0” Write

From Master to Slave

From Slave to Master

A = acknowledge (SDA LOW)

S = START condition

P = STOP condition

Read command consists of dummy write to set the proper address of a register followed by a real read

sequence.

Slave Address

S

R/W

A

A

Register Address

Slave Address

7 bits

1

1

1

1

1

8 bits

1

“0” Write

From Master to Slave

From Slave to Master

A = acknowledge (SDA LOW)

S = START condition

P = STOP condition

Sr = Repeated Start

1

1

R/W

A

A

P

Register Address

Sr

7 bits

8 bits

“1” Write

1

The master sends a “Repeated Start” after sending the register address and before resending the slave address.

The “Repeated Start” is defined as SDA transition from 1 to 0 with SCL high.

7.12.2

The address is composed as below:

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0

0

0

0

1

ADD1

ADD0

R/W

STPD01

Bus timing

DS13473 - Rev 1

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