MCP3564-ESLASHST datasheet(37/108 Pages) MICROCHIP

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DS20006181C-page 37

MCP3561/2/4

The default value of the bit stream after a Reset or a

power-up is ‘0011’; it is equivalent to a 0V input for the

ADC. After each ADC reset and restart (see

Section 5.15 “A/D Conversions’ Automatic Reset

and Restart Feature”), the bit stream output is also

reset and restarted, and the IRQ/MDAT is kept equal to

logic high during the two MCLK clock periods needed

for the synchronization. After these two clock periods,

the bit stream will be provided on the IRQ/MDAT pin

and the first value will be the default value.

FIGURE 5-3:

MDAT Serial Outputs

Depending on the Modulator Output Code.

5.4.3

BOOST MODES

The Delta-Sigma modulator includes a programmable

biasing circuit in order to further adjust the power

consumption to the sampling speed applied through

the MCLK. This can be programmed through the

BOOST[1:0] bits in the CONFIG2 register. The

different BOOST settings are applied to the entire

modulator circuit, including the voltage reference

buffers. The settings of the BOOST[1:0] bits are

described in Table 5-5.

The maximum achievable Analog Master Clock

(AMCLK) speed, the maximum sampling frequency

(DMCLK) and the maximum achievable data rate

(DRCLK) are highly dependent on the BOOST[1:0] and

GAIN[2:0] settings. A higher BOOST setting allows the

circuit’s bandwidth to be increased and allows a higher

analog master clock rate which will then increase the

baseband of the input signals to be converted. The

digital gain (which is enabled at 32x and 64x gains) has

no influence on the achievable bandwidth.

A typical dependency of the bandwidth depending on

the gain for each BOOST setting combination is shown

from Figure 2-20 to Figure 2-23. Typically, a larger gain

setting requires a higher BOOST setting in order to

achieve the same bandwidth performance.

Figure 2-24 shows the behavior of the achievable

bandwidth at BOOST = 1x with AVDD corner cases.

Since the BOOST settings vary, the internal slew rate

of the modulator components, using a lower VREF

value, will improve the bandwidth if low BOOST set-

tings are used and show a bandwidth behavior that is

too limited.

TABLE 5-4:

DELTA-SIGMA MODULATOR

OUTPUT BIT STREAM CODING

COMP[3:0]

Code

Modulator

Output Code

(Decimal)

MDAT

Serial

Stream

Equivalent

VREF

Voltage

1111

+VREF

0111

+VREF/2

0011

0001

-1

0001

-VREF/2

0000

-2

0000

-VREF

AMCLK

tDOMDAT

MDAT

(code = +2)

MDAT

(code = +1)

MDAT

(code = 0)

MDAT

(code = -1)

MDAT

(code = -2)

COMP[3]

C OMP[2]

COMP[1]

C OMP[0]

tDOMDAT tDOMDAT tDOMDAT tDOMDAT

TABLE 5-5:

BOOST SETTINGS

DESCRIPTION

BOOST[1:0]

Bias Current

x0.5

x0.66

x1 (default)

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