MCP3564-ESLASHST datasheet(71/108 Pages) MICROCHIP

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DS20006181C-page 71

MCP3561/2/4

6.6

Locking/Unlocking Register Map

Write Access

The MCP3561/2/4 digital interface includes an

advanced security feature that allows locking or unlock-

ing the register map write access. This feature prevents

the miscommunication that can corrupt the desired

configuration of the device, especially an SPI read

becoming an SPI write because of the noisy

environment.

The last register address of the incremental write loop

(0xD: LOCK) contains the LOCK[7:0] bits. If these bits

are equal to the password value (0xA5), the register

map write access is not locked. Any write can take

place and the communications are not protected. The

devices are, by default after POR, in an Unlocked state

(LOCK[7:0] = 0xA5).

When the LOCK[7:0] bits are not equal to 0xA5, the

and therefore, the full device configuration is write-

protected. Any write to an address other than 0xD will

yield no result. All the register addresses, except the

address 0xD, become read-only. In this case, if the user

wants to change the configuration, the LOCK[7:0] bits

have to be reprogrammed back to 0xA5 before sending

the desired Write command.

The LOCK[7:0] bits are located in the last register of the

Incremental Write address loop, so the user can pro-

gram the entire register map, starting from 0x1 to 0xD,

within one continuous write sequence and then lock the

configuration at the end of the sequence by writing all

zeros (for example) in the 0xD address.

6.7

Detecting a Configuration Change

through CRC-16 Checksum on the

Interrupt Flag

In order to prevent internal corruption and to provide

additional security on the register map configuration, the

MCP3561/2/4 devices include an automatic and contin-

uous CRC checksum calculation on the full register map

Configuration bits. This calculation is not the same as

the communication CRC checksum described in

Section 6.5

“Securing

Read

Communications

through CRC-16 Checksum”.

This calculation takes the contents of the register map,

from addresses 0x1 to 0xF, and produces a checksum

which is held in the CRCCFG[15:0] bits located in the

CRCCFG register (address: 0xF). The CRC checksum

for the register map uses the 16-bit CRC-16 ANSI poly-

nomial as defined in the IEEE 802.3 standard:

x16 +x15 +x2 +1.

Since this feature is intended to protect the configura-

tion of the device, this calculation is run continuously

only when the register map is locked (LOCK[7:0]),

which is different than 0xA5 (see Section 6.6

“Locking/Unlocking

Map

Write

Access”). If the register map is unlocked (for example

after POR), the CRCCFG[15:0] bits are cleared and no

CRC is calculated.

The

DR_STATUS,

CRCCFG_STATUS

and

POR_STATUS bits are set to ‘1’ (default) and the

CRCCFG[15:0] bits are set to ‘0’ (default) for this calcu-

lation, as they could vary and lead to unwanted CRC

errors.

After the DR_STATUS, CRCCFG_STATUS and

POR_STATUS bits are cleared (with a read on the IRQ

be verified by reading all registers in an incremental

read sequence and by using the CRC communication.

At the second incremental read loop, the checksum

provided by the CRC communication must be equal to

all zeros if the checksum on the register map is correct.

The checksum will be calculated for the first time in

11 DMCLK periods. This first value will then be the

reference checksum value and will be latched internally

until an unlocking of the register map occurs. The

checksum will then be calculated continuously every

11 DMCLK periods and checked against the reference

checksum.

If the checksum is different than the reference, an inter-

rupt flag will be generated on the CRCCFG_STATUS

bit within the STATUS byte on SDO, on the

CRCCFG_STATUS bit in the IRQ register and on the

IRQ output pin. The interrupt flag is maintained on all

three mechanisms until the register map write access

is unlocked.

When the part write access is unlocked, the interrupt on

the IRQ pin clears immediately and the two other inter-

rupt mechanisms are cleared when the interrupt is read

(read STATUS byte or read IRQ register). The CRC

interrupt can occur even if the IRQ pin is configured as

the MDAT modulator output. In this case, the interrupt

stays present and forces a logic low output on this pin

as long as the LOCK[7:0] register bits are locked

(LOCK[7:0] = 0xA5).

At power-up, the interrupt is not present and the

writing its configuration, the user needs to lock the reg-

ister map (for example, by writing 0x00 in the LOCK

bits) to be able to use the interrupt flag and to calculate

the checksum of the register map.

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