MCP3564-ESLASHST datasheet(69/108 Pages) MICROCHIP

69 / 108 page

 2019-2021 Microchip Technology Inc.

DS20006181C-page 69

MCP3561/2/4

For continuous reading of ADCDATA in SPI Mode 0,0,

once the data have been completely read after a data

ready interrupt, the SDO pin takes the MSb value of the

previous data at the end of the reading (falling edge of

the last SCK clock). If SCK stays Idle at logic low (by

definition of Mode 0,0), the SDO pin will be updated at

the falling edge of the next data ready pulse (synchro-

nously with the IRQ pin falling edge with an output

timing of tDODR) with the new MSb of the data corre-

sponding to the data ready pulse. This mechanism

allows the device to continuously read ADC data

outputs seamlessly, even in SPI Mode (0,0).

In SPI Mode (1,1), the SDO pin stays in the last state

(LSb of previous data) after a complete reading, which

also allows seamless Continuous Read mode.

The ADC output data can only be properly read after a

tDODR time, after the data ready interrupt comes on the

IRQ pin. The tDODR timing is shorter than the time

necessary to input a command on the SDI pin, which

ensures proper reading when a new Read command is

triggered by the data ready interrupt. In case of contin-

uous reading (with CS pin kept logic low), the tDODR

timing must be carefully handled by the MCU, but in

general, the interrupt service time is much longer than

the tDODR timing. Retrieving a data ready interrupt by

reading the STATUS byte or reading the IRQ register

automatically ensures that the tDODR timing is

respected.

6.5

Securing Read Communications

through CRC-16 Checksum

Since some applications can generate or receive large

EMI/EMC interferences and large transient spikes, it is

helpful to secure SPI communications as much as

possible, to maintain data integrity and desired

configurations during the application’s lifetime.

The communication data on the SDO pin can be

secured through the insertion of a Cyclic Redundancy

Check (CRC) checksum at the end of each read

sequence. The CRC checksum on communications

can be enabled or disabled through the EN_CRCCOM

bit in the CONFIG3 register. The CRC message

ensures the integrity of the read sequence bits

transmitted on the SDO pin.

The CRC checksum in the MCP3561/2/4 devices uses

the 16-bit CRC-16 ANSI polynomial as defined in the

IEEE 802.3 standard: x16 +x15 +x2 +1.

This polynomial can also be noted as 0x8005. CRC-16

detects all single and double-bit errors, all errors with

an odd number of bits, all burst errors of 16 bits in

length or less and most errors for longer bursts. This

allows an excellent coverage of the SPI communication

errors that can occur in the system, and heavily

reduces the risk of a miscommunication, even under

noisy environments.

When enabled, the CRC checksum (CRCCOM[15:0])

is propagated on SDO after each read communication

sequence.

In case of a Static Read command, the checksum is

propagated after each register read. In case of an

Incremental Read command, the checksum is propa-

gated after the last register read in the register map

(address: 0xF). Figure 6-11 and Figure 6-12 show

typical read communications in Static Read and

Incremental Read modes, respectively, when the

EN_CRCCOM bit is enabled. Since the STATUS byte

is propagated on SDO, it is part of the first message,

and therefore, it is included in the calculation of the first

checksum. For subsequent checksum calculations, the

message only contains the registers that are effectively

read in between two checksums.

The CRC-16 format displayed on the SDO pin depends

on the CRC_FORMAT bit in the CONFIG3 register (see

Figure 6-10). It can have a 16-bit or 32-bit format to be

compatible with both 16-bit and 32-bit MCUs. The

CRCCOM[15:0] bits calculated by the device do not

depend on the format (the device always calculates a

16-bit only CRC checksum).

FIGURE 6-10:

CRC Format Table for Read

Communications.

The CRC calculation computed by the device is fully

compatible with the CRC hardware contained in the

Direct Memory Access (DMA) of the PIC24 and PIC32

MCU product lines. The CRC message that should be

considered in the PIC® device DMA is the concatena-

tion of the read sequence and its associated

checksum. When the DMA CRC hardware computes

this extended message, the resulted checksum should

be 0x0000. Any other result indicates that a

miscommunication has occurred and that the current

communication sequence should be stopped and

restarted.

CRCCOM[15:0]

0x0000

CRC_FORMAT = 0: 16-Bit

(Default)

CRC_FORMAT = 1: 32-Bit

MCP3564-E/ST 数据表(PDF) 69 Page - Microchip Technology

MCP3564-E/ST 数据表(HTML) 69 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载