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MCP3564-E/ST 数据表(PDF) 62 Page - Microchip Technology

部件名 MCP3564-E/ST
功能描述  Two/Four/Eight-Channel, 153.6 ksps, Low-Noise 24-Bit Delta-Sigma ADCs
PDF  108 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP3564-E/ST 数据表(HTML) 62 Page - Microchip Technology

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MCP3561/2/4
DS20006181C-page 62
 2019-2021 Microchip Technology Inc.
These three Interrupt Status bits are independent of the
two other interrupt mechanisms (IRQ pin and IRQ
register) and are cleared each time the STATUS byte is
fully clocked. This enables the polling on the STATUS
byte as a possible interrupt management solution with-
out requiring to connect the IRQ pin in the system. All
Status bit values are latched together just after the
device address has been correctly recognized by the
chip. Any interrupt happening after the two first Status
bits have been clocked out will appear in the STATUS
byte of the subsequent communication sequence.
Figure 6-2
represents
the
beginning
of
each
communication with both COMMAND and STATUS
bytes depicted. After the STATUS byte is propagated,
the SDO pin will be placed in high-impedance for Fast
commands or Write commands and will transfer data
bytes for Read commands as long as the CS pin stays
logic low.
FIGURE 6-2:
SPI Communication Start (COMMAND on SDI and STATUS on SDO) when the
Device Address Matches/Does Not Match CMD[7:6].
Don’t Care
SCK
SDI
SDO
CS
High-Z
Device Latches SDI on Rising Edge
SPI Mode 0,0
SPI Mode 1,1
0
Device
Address
Register
Address
Command
Type
Device
Address ACK
Interrupts
Status
High-Z
0
Device Address
Matches CMD[7:6]
High-Z
SDO
Device Address
does not Match
CMD[7:6]
Device Latches SDO on Falling Edge



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