LP3971 datasheet(19/42 Pages) NSC

19 / 42 page

2C Register Definitions (Continued)

Bit

Access

Name

Description

WUPT

TEST_JIG Pin Wake Up Status

0 = No wake up event

1 = Wake up event

WUPS

SPARE Pin Wake Up Status

0 = No wake up event

1 = Wake up event

SYSTEM CONTROL REGISTER 1 (SCR1) 8h’07

Bit

Designation

BPSEN

Reserved

SENDL

FPWM3

FPWM2

FPWM1

ECEN

Reset Value

Note: Gray denotes EPROM programmable registers for default value.

SYSTEM CONTROL REGISTER 1 (SCR1) 8h’07 DEFINITIONS

Bit

Access

Name

Description

R/W

BPSEN

Bypass System enable safety Lock. Prevents activation of PWR_EN when SYS_EN is low.

0 = PWR_EN “AND” with SYS_EN signal

1 = PWR_EN independent of SYS_EN

Reserved

5:4

R/W

SENDL

Delay time for High Voltage Power Domains LDO2, LDO3, LDO4, Buck2, and Buck3 after

activation of SYS_EN. VCC_LDO1 has no delay.

Data Code

Delay mS

Notes

2h’0

0.0

Default for “B”

2h’1

0.5

2h’2

1.0

Default for “A”

2h’3

1.4

R/W

FPWM3

Buck 3 PWM/PFM Mode Select

0 - Auto Switch between PFM and PWM operation

1 - PWM Mode Only will not switch to PFM

R/W

FPWM2

Buck 2 PWM/PFM Mode Select

0 - Auto Switch between PFM and PWM operation

1 - PWM Mode Only will not switch to PFM

R/W

FPWM1

Buck 1 PWM/PFM Mode Select

0 - Auto Switch between PFM and PWM operation

1 - PWM Mode Only will not switch to PFM

R/W

ECEN

External Clock Select

0 = Internal Oscillator clock for Buck Converters

1 = External 13 MHz Oscillator clock for Buck Converters

LP3971 数据表(PDF) 19 Page - National Semiconductor (TI)

LP3971 数据表(HTML) 19 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表下载

链接网址

LP3971 数据表(PDF) 19 Page - National Semiconductor (TI)

LP3971 数据表(HTML) 19 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表 下载

链接网址

数据表下载