SHUTDOWN MODE

During shutdown the PFET switch, reference, control and

bias circuitry of the converters are turned off. The NFET

switch will be on in shutdown to discharge the output. When

the converter is enabled, soft start is activated. It is recom-

mended to disable the converter during the system power up

and undervoltage conditions when the supply is less than

2.8V.

SOFT START

The buck converter has a soft-start circuit that limits in-rush

current during start-up. During start-up the switch current

limit is increased in steps. Soft start is activated only if EN

goes from logic low to logic high after V

start is implemented by increasing switch current limit in

steps of 213 mA, 425 mA, 850 mA and 1700 mA (typ. Switch

current limit). The start-up time thereby depends on the

output capacitor and load current demanded at start-up.

Typical start-up times with 10 µF output capacitor and 1000

mA load current is 390 µs and with 1 mA load current its

295 µs.

LDO - LOW DROP OUT OPERATION

The LP3971 can operate at 100% duty cycle (no switching;

PMOS switch completely on) for low drop out support of the

output voltage. In this way the output voltage will be con-

trolled down to the lowest possible input voltage. When the

device operates near 100% duty cycle, output voltage ripple

is approximately 25 mV. The minimum input voltage needed

to support the output voltage is

V

LOAD

Load Current

DSON, PFET

Drain to source resistance of PFET

switch in the triode region

INDUCTOR

Inductor resistance

BUCK CONVERTER EFFICIENCY

V

V

I

EFF(%)

3.6

1.4

100

85

3.6

1.4

500

89

3.6

1.4

1000

84

3.6

1.4

1500

78

V

V

I

EFF(%)

3.6

3.3

100

92

3.6

3.3

500

96

3.6

3.3

1000

93

3.6

3.3

1500

90

V

V

I

EFF(%)

3.6

1.8

100

85

3.6

1.8

500

91

3.6

1.8

1000

87

3.6

1.8

1500

82

I

I

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can

only be changed when CLK is LOW.

20180714

I

START and STOP bits classify the beginning and the end of

the I

transitioning from HIGH to LOW while SCL line is HIGH.

STOP condition is defined as the SDA transitioning from

LOW to HIGH while SCL is HIGH. The I

generates START and STOP bits. The I

to be busy after START condition and free after STOP con-

dition. During data transmission, I

repeated START conditions. First START and repeated

START conditions are equivalent, function-wise.

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