LP3971 datasheet(34/42 Pages) NSC

34 / 42 page

LP3971 Controls (Continued)

to be active low or high (SPARE bit, Default is active low ‘1’).

A reason for wakeup event can be read through I

2C compat-

ible interface also. Additionally wakeup inputs have 30 ms

de-bounce filtering. Furthermore PWR_ON have distinguish-

ing between short and long (

∼1s) pulses (push button input).

LP3971 also has an internal Thermal Shutdown early warn-

ing that generates a wakeup to the system also. This is

generated usually at 125˚C.

20180719

WAKEUP Register Bits

Reason for WAKEUP

WUP0

SPARE

WUP1

TEST_JIG

WUP2

PWR_ON Short Pulse

WUP3

PWR_ON Long Pulse

TSD_EW

TSD Early Warning

INTERNAL THERMAL SHUTDOWN PROCEDURE

Thermal shutdown is build to generate early warning (typ.

125˚C) which triggers the EXT_WAKEUP for the processor

acknowledge. When a thermal shutdown triggers (typ.

160˚C) the PMU will reset the system until the device cools

down.

BATTERY SWITCH AND BACK UP BATTERY CHARGER

When Back-Up battery is connected but main battery re-

moved or voltage too low, LP3971 uses Back-Up Battery for

generating LDO_RTC voltage. When Main Battery is avail-

able the battery switch changes main battery for LDO_RTC

voltage. When Main battery voltage is too low or removed

nBATT_FLT is asserted to system acknowledge. If no back

up battery exists, the battery switch to back up can be

switched off by nBU_BAT_EN bit. User can set the battery

fault determination voltage and battery charger termination

voltage via I

2C compatible interface. Enabling of back up

battery

charger

can

done

via

serial

interface

(nBAT_CHG_EN)

external

charger

enable

(nCHG_EN). Pin 29 is set as external charger enable input

by default.

LP3971 数据表(PDF) 34 Page - National Semiconductor (TI)

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