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LP3971 数据表(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
部件名 LP3971
功能描述  POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS
PDF  42 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

LP3971 数据表(HTML) 4 Page - National Semiconductor (TI)

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Pin Descriptions
Pin #
Name
I/O
Type
Description
1
PWR_ON
I
D
CPU Wakeup input
2
nTEST_JIG
I
D
CPU Wakeup input
3
SPARE
I
D
CPU Wakeup input
4
EXT_WAKEUP
O
D
CPU Wakeup output
5
FB1
I
A
Buck1 Feedback
6V
IN
I
P
Battery Input (Internal circuitry and LDO1–3 power input)
7V
OUT LDO1
O
P
LDO1 output
8V
OUT LDO2
O
P
LDO2 output
9
nRSTI
I
D
Reset Input
10
GND1
G
G
Ground
11
V
REF
O
A
Bypass Cap. for reference
12
V
OUT LDO3
O
P
LDO3 output
13
V
OUT LDO4
O
P
LDO4 output
14
V
IN LDO4
I
P
Input power for LDO4
15
V
IN BUBATT
I
P
Back Up Battery input
16
V
OUT LDO_RTC
O
P
LDO_RTC output
17
nBATT_FLT
O
D
Main Battery fault output
18
PGND2
G
G
Buck2 NMOS Power Ground
19
SW2
O
P
Buck2 Output
20
V
IN Buck2
I
P
Buck2 battery input
21
SDA
I/O
D
I
2C Data
22
SCL
I
D
I
2C Clock
23
FB2
I
A
Buck2 Feedback
24
nRSTO
O
D
Reset output
25
V
OUT LDO5
O
P
LDO5 output
26
V
IN LDO5
I
P
Input power for LDO5
27
VDDA
I
P
Analog Power
28
FB3
I
A
Buck3 Feedback
29
GPIO1/nCHG_EN
I/O
D
General Purpose I/O/Ext. backup battery charger enable
30
GPIO2
I/O
D
General Purpose I/O
31
V
IN Buck3
I
P
Buck3 battery input
32
SW3
O
P
Buck3 Output
33
PGND3
G
G
Buck3 NMOS Power Ground
34
BGND1,2,3
G
G
Bucks 1, 2 and 3 analog Ground
35
SYNC
I
D
Bucks external clock input
36
SYS_EN
I
D
High voltage domain enable
37
PWR_EN
I
D
Low Voltage domain enable
38
PGND1
G
G
Buck1 NMOS Power Ground
39
SW1
O
P
Buck1 Output
40
V
IN Buck1
I
P
Buck1 battery input
A: Analog Pin
D: Digital Pin
G: Ground Pin
P: Power Pin
I: Input Pin
I/O: Input/Output Pin
O: Output Pin
Note: In this document active low logic items are prefixed with a lowercase “n”
www.national.com
4



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