LP3971 datasheet(38/42 Pages) NSC

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Application Note (Continued)

Code Start Power on Timing

20180722

POWER-ON TIMING

Symbol

Description

Min

Typ

Max

Units

Delay from VCC_RTC assertion to nRSTO de-assertion

Delay from nRST de-assertion to SYS_EN assertion

Delay from SYS_EN assertion to PWR_EN assertion

125

Delay from PWR_EN assertion to nRSTO de-assertion

125

LP3971 & PXA27x RESET SEQUENCE

Hardware Reset Sequence

Hardware reset initiates when the nRSTI signal is asserted

(low). Upon assertion of nRST the processor enters hard-

ware reset state. The LP3971 holds the nRST low long

enough (50ms typ.) to allow the processor time to initiate the

reset state.

Reset Sequence

nRSTI is asserted

If V

BATT is above the set point the PMIC de-asserts

nBATT_FLT to indicate system power (V

IN) is available.

nRSTO is asserted and will de-asserts after a minimum

of 50 mS.

The Applications processor asserts SYS_EN, the

LP3971 enables the system high-voltage power sup-

plies. The Applications processor starts its countdown

timer set to 125 mS.

The LP3971 enables the high-voltage power supplies.

Countdown timer expires; the Applications processor

asserts PWR_EN to enable the low-voltage power sup-

plies. The processor starts the countdown timer set to

125 mS period.

The Applications processor asserts PWR_EN, the

LP3971 enables the low-voltage regulators.

Countdown timer expires; If enabled power domains are

OK (I

2C read) the power up sequence continues by

enabling the processors 13 MHz oscillator and PLL’s.

The Applications processor begins the execution of

code.

LP3971 数据表(PDF) 38 Page - National Semiconductor (TI)

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