7

AT25DF256

DS-25DF256–035D–2/2017

7.

Read Commands

7.1

Read Array

The Read Array command can be used to sequentially read a continuous stream of data from the device by simply

providing the clock signal once the initial starting address is specified. The device incorporates an internal address

counter that automatically increments every clock cycle.

Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each opcode depends on the

maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock

To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be

clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the

starting address location of the first byte to read within the memory array. Following the three address bytes, an

additional dummy byte needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.

After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in, additional clock cycles

will result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte

(007FFFh) of the memory array has been read, the device will continue reading back at the beginning of the array

(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.

Deasserting the CS pin will terminate the read operation and put the SO pin into high-impedance state. The CS pin can

be deasserted at any time and does not require a full byte of data be read.

Write Status Register Byte 2

31h

0011 0001

Up to 104 MHz

0

0

1

Miscellaneous Commands

Reset

F0h

1111 0000

Up to 104 MHz

0

0

1 (D0h)

Read Manufacturer and Device ID

9Fh

1001 1111

Up to 104 MHz

0

0

1 to 4

Read ID (Legacy Command)

15h

0001 0101

Up to 104 MHz

0

0

2

Deep Power-Down

B9h

1011 1001

Up to 104 MHz

0

0

0

Resume from Deep Power-Down

ABh

1010 1011

Up to 104 MHz

0

0

0

Ultra Deep Power-Down

79h

0111 1001

Up to 104 MHz

0

0

0

Table 6-1.

Command Listing

Command

Opcode

Clock

Frequency

Address

Bytes

Dummy

Bytes

Data

Bytes