12

AT25DF256

DS-25DF256–035D–2/2017

8.4

Chip Erase

The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase

command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit

of the Status Register to a logical “1” state.

Three opcodes (60h, 62h, and C7h) can be used for the Chip Erase command. There is no difference in device

functionality when utilizing the three opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the

three opcodes must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to

be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the

device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a

The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if the

memory array is in the protected state, then the Chip Erase command will not be executed, and the device will return to

the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical

“0” state if the CS pin is deasserted on uneven byte boundaries or if the memory is in the protected state.

While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device

determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status

Register will be reset back to the logical “0” state.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If

an erase error occurs, it will be indicated by the EPE bit in the Status Register.

Figure 8-4. Chip Erase

9.

Protection Commands and Features

9.1

Write Enable

The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state.

The WEL bit must be set before a Byte/Page Program, erase, Program OTP Security Register, or Write Status Register

command can be executed. This makes the issuance of these commands a two step process, thereby reducing the

chances of a command being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to

the issuance of one of these commands, then the command will not be executed.

To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the

device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.

When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The complete opcode must

be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte

SCK

CS

SI

SO

MSB

23

1

0

CCCCCCCC

67

5

4

OPCODE

HIGH-IMPEDANCE