24

AT25DF256

DS-25DF256–035D–2/2017

When the device is in the Deep Power-Down mode, all commands including the Read Status Register command will be

ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be ignored, the

mode can be used as an extra protection mechanism against program and erase operations.

Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode of B9h,

and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the

The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an

even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode

once the CS pin is deasserted. In addition, the device will default to the standby mode after a power-cycle.

The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is

in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been

completed in order for the device to enter the Deep Power-Down mode.

Figure 12-3. Deep Power-Down

12.4 Resume from Deep Power-Down

In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down

command must be issued. The Resume from Deep Power-Down command is the only command that the device will

recognized while in the Deep Power-Down mode.

To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode of ABh must be clocked into

the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted,

the device has returned to the standby mode, normal command operations such as Read Array can be resumed.

If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an even

byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down

mode.

SCK

CS

SI

SO

MSB

23

1

0

10111001

67

5

4

OPCODE

HIGH-IMPEDANCE

Standby Mode Current

Active Current

Deep Power-Down Mode Current