18

AT25DF256

DS-25DF256–035D–2/2017

Notes:

1. Only bits 7 and 2 of the Status Register can be modified when using the Write Status Register command.

2. R/W = Readable and writable

R = Readable only

11.1.1 BPL Bit

The BPL bit is used to control whether the Block Protection (BP0) bit can be modified or not. When the BPL bit is in the

locked in the current protected or unprotected state.

When the BPL bit is in the logical “0” state, the BP0 bit will be unlocked and can be modified. The BPL bit defaults to the

logical “0” state after device power-up.

The BPL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then the BPL

bit may only be changed from a logical “0” (BP0 bit unlocked) to a logical “1” (BP0 bit locked). In order to reset the BPL bit

back to a logical “0” using the Write Status Register command, the WP pin will have to first be deasserted.

The BPL and BP0 bits are the only bits of the Status Register that can be user modified via the Write Status Register

command.

11.1.2 EPE Bit

The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte

during the erase or program operation did not erase or program properly, then the EPE bit will be set to the logical “1”

state. The EPE bit will not be set if an erase or program operation aborts for any reason such as an attempt to erase or

program the memory when it is protected or if the WEL bit is not set prior to an erase or program operation. The EPE bit

will be updated after every erase and program operation.

11.1.3 WPP Bit

The WPP bit can be read to determine if the WP pin has been asserted or not.

11.1.4 BP0 Bit

modified to change the state of the software protection to allow the entire memory array to be protected or unprotected.

When the BP0 bit is in the logical “0” state, then the entire memory array is unprotected. When the BP0 bit is in the logical

“1” state, then the entire memory array is protected against program and erase operations.

11.1.5 WEL Bit

The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state,

the device will not accept any Byte/Page Program, erase, Program OTP Security Register, or Write Status Register

3

RES

Reserved for future use

R

0

Reserved for future use.

2

BP0

Block Protection

R/W

0

Entire memory array is unprotected.

1

Entire memory array is protected.

1

WEL

Write Enable Latch Status

R

0

Device is not write enabled (default).

1

Device is write enabled.

0

RDY/BSY

Ready/Busy Status

R

0

Device is ready.

1

Device is busy with an internal operation.

Table 11-1. Status Register Format

Name

Description