16

AT25DF256

DS-25DF256–035D–2/2017

“0”. After the address bytes have been clocked in, data can then be clocked into the device and will be stored in the

internal buffer.

If the starting memory address denoted by A23-A0 does not start at the beginning of the OTP Security Register memory

space (A5-A0 are not all 0), then special circumstances regarding which OTP Security Register locations to be

programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the 64-byte user-

programmable space will wrap around back to the beginning of the OTP Security Register. For example, if the starting

address denoted by A23-A0 is 00003Eh, and three bytes of data are sent to the device, then the first two bytes of data

will be programmed at OTP Security Register addresses 00003Eh and 00003Fh while the last byte of data will be

programmed at address 000000h. The remaining bytes in the OTP Security Register (addresses 000001h through

00003Dh) will not be programmed and will remain in the erased state (FFh). In addition, if more than 64 bytes of data are

sent to the device, then only the last 64 bytes sent will be latched into the internal buffer.

When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the

appropriate OTP Security Register locations based on the starting address specified by A23-A0 and the number of data

bytes sent to the device. If less than 64 bytes of data were sent to the device, then the remaining bytes within the OTP

Security Register will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is

The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is

deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device

will abort the operation and the user-programmable portion of the OTP Security Register will not be programmed. The

WEL bit in the Status Register will be reset back to the logical “0” state if the OTP Security Register program cycle aborts

due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven

byte boundaries, or because the user-programmable portion of the OTP Security Register was previously programmed.

While the device is programming the OTP Security Register, the Status Register can be read and will indicate that the

time to determine if the data bytes have finished programming. At some point before the OTP Security Register

programming completes, the WEL bit in the Status Register will be reset back to the logical “0” state.

If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte user

programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed again.

The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the contents of

the buffer will be altered from its previous state when this command is issued.

Figure 10-1. Program OTP Security Register

10.2 Read OTP Security Register

The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum

of 77h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in

to specify the starting address location of the first byte to read within the OTP Security Register. Following the three

address bytes, two dummy bytes must be clocked into the device before data can be output.

SCK

CS

SI

SO

MSB

MSB

23

1

0

10011011

67

5

49

839

37 38

33

36

35

34

31 32

29 30

OPCODE

HIGH-IMPEDANCE

AA

AAA

A

MSB

DDDDDDD

D

ADDRESS BITS A23-A0

DATA IN BYTE 1

MSB

DDDDDDD

D

DATA IN BYTE n