20

AT25DF256

DS-25DF256–035D–2/2017

Figure 11-1. Read Status Register

11.2 Write Status Register

The Write Status Register command is used to modify the BPL bit and the BP0 bit of the Status Register. Before the

Write Status Register command can be issued, the Write Enable command must have been previously issued to set the

WEL bit in the Status Register to a logical “1”.

To issue the Write Status Register command, the CS pin must first be asserted and the opcode of 01h must be clocked

into the device followed by one byte of data. The one byte of data consists of the BPL bit value, four don’t care bits, the

BP0 bit value, and two additional don’t care bits (see Table 11-3). Any additional data bytes that are sent to the device

will be ignored. When the CS pin is deasserted, the BPL bit and the BP0 bit in the Status Register will be modified, and

the WEL bit in the Status Register will be reset back to a logical “0”. The value of BP0 and the state of the BPL bit and the

WP pin before the Write Status Register command was executed (the prior state of the BPL bit and the state of the WP

pin when the CS pin is deasserted) will determine whether or not software protection will be changed. Please refer to

Section 9.4, “Protected States and the Write Protect Pin” on page 14 for more details.

The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of

the BPL and BP0 bits will not change, memory protection status will not change, and the WEL bit in the Status Register

will be reset back to the logical “0” state.

If the WP pin is asserted, then the BPL bit can only be set to a logical “1”. If an attempt is made to reset the BPL bit to a

logical “0” while the WP pin is asserted, then the Write Status Register Byte command will be ignored, and the WEL bit in

the Status Register will be reset back to the logical “0” state. In order to reset the BPL bit to a logical “0”, the WP pin must

be deasserted.

SCK

CS

SI

SO

MSB

23

1

0

00000101

67

5

410 11

9

812

21 22

17

20

19

18

15 16

13 14

23 24

OPCODE

MSB

MSB

DDDDDD

DD

D

D

MSB

DDDDDD

D

D

STATUS REGISTER BYTE1

STATUS REGISTER BYTE2

HIGH-IMPEDANCE

Table 11-3. Write Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BPL

X

X

X

X

BP0

X

X