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ASL5015FHN 数据表(PDF) 44 Page - NXP Semiconductors |
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ASL5015FHN 数据表(HTML) 44 Page - NXP Semiconductors |
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44 / 69 page  NXP Semiconductors ASL5xxxyHz Matrix LED Controller (MLC) ASL5xxxyHz All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 2.1 — 5 February 2019 44 / 69 • PWM frequency selection (244 Hz or 488 Hz) • Slew rate control per block (individual) • Switching phase shifting sequences for the different floating blocks • Limp Home mode sequence • Communication baud rate • Open-circuit detection threshold • Single / Multiple MLCs (internal push/pull configuration) • LED calibration / scaling factor (5-bits per channel) • Overtemperature warning (OTW1 and OTW2) thresholds • Standby mode (full / partial networking) • MTP Lock Key and counter • Short-circuit blanking time selection • Charge pump fail-safe operation mode (CPFSO) • Free customer data (~ 480-bit) • Internal configuration (not accessible by user) The MTP can be programmed at the end of the production line (once the MLC is populated on the PCB). The CAN interface can be used to program all the values in the registers. Table 34 shows the registers to write and read from the MTP, together with a detailed write and read sequence. Table 34. MTP Read/Write Address Register D7 D6 D5 D4 D3 D2 D1 D0 3Dh (R/W) MTP control unused MTP Register Address 3Eh (R/W) MTP Write D1 MTP Write Data D1 [7:0] 3Fh (R/W) MTP Write D2 MTP Write Data D2 [7:0] 40h (R) MTP Read D1 MTP Read Data D1 [7:0] 41h (R) MTP Read D2 MTP Read Data D2 [7:0] Write and read process flow charts are available in the application notes. 14.1 MTP memory map Table 35. MTP memory map MTP Registers (16 bits registers)[1][2] No. Bits Block 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Add ress 0 0 00h 16 1 01h ~ reserved[3] ~ 112 7 MTP Write Counter0[4] IC Version[4] 07h ~ ~ 880 55 reserved 37h 896 56 A 38h 912 57 B 39h 928 58 C 3Ah 944 59 Value has no impact[5] Curve 0 coefficients D 3Bh |
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