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ASL5015FHN 数据表(PDF) 47 Page - NXP Semiconductors

部件名 ASL5015FHN
功能描述  Matrix LED Controller (MLC)
PDF  69 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

ASL5015FHN 数据表(HTML) 47 Page - NXP Semiconductors

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NXP Semiconductors
ASL5xxxyHz
Matrix LED Controller (MLC)
ASL5xxxyHz
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 2.1 — 5 February 2019
47 / 69
Register
Bit D3
Bit D2
Bit D1
Bit D0
[V/µs]
1
0
1
1
3,2
1
1
0
0
3,8
1
1
0
1
4,5
1
1
1
0
5,5
1
1
1
1
6,8
Table 38. Phase shifting sequence in the different floating blocks
Register
Block [bits] (switches)[1]
Conf_1
Conf_2
Default
Block 1 [8:9] (SW0 – SW3)
X
X
00
Block 2 [8:9] (SW4 – SW7)
X
X
01
Block 3 [8:9] (SW8 – SW11)
X
X
10
58h (PS1)
59h (PS2)
5Ah (PS3)
5Bh (PS4)
Block 4 [8:9] (SW12 – SW15)
X
X
11
Conf_1
Conf_2
Channel / Phases
0
0
1, 2 and 3
0
1
4, 5 and 6
1
0
7, 8 and 9
1
1
10, 11 and 12
[1]
When blocks are in parallel configuration, the phase shifting sequence must be the same, since both switches associated
to the same light source must switch at the same time.
Table 39. Limp Home mode selection (58h, 59h, 5Ah and 5Bh)
Bits
LHx
Selection
0
LED OFF
7 to 5
1
LED ON
Table 40. Short circuit timer (blanking time after duty cycle rising edge)
Register
Bit D4
Protocol
0
16 µs (default)
60h
1
32 µs
Table 41. Data rate selection
Register
Bit D3
Bit D2
Data rate
0
0
125 Kb/sec
0
1
250 Kb/sec
60h
1
0
500 Kb/sec (default)



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