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ASL5015FHN 数据表(PDF) 68 Page - NXP Semiconductors

部件名 ASL5015FHN
功能描述  Matrix LED Controller (MLC)
PDF  69 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

ASL5015FHN 数据表(HTML) 68 Page - NXP Semiconductors

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NXP Semiconductors
ASL5xxxyHz
Matrix LED Controller (MLC)
ASL5xxxyHz
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 2.1 — 5 February 2019
68 / 69
Tables
Tab. 1.
Orderable part variations ...................................4
Tab. 2.
Pin description ...................................................7
Tab. 3.
Pin description ...................................................9
Tab. 4.
Curve selection, auto-bit, shift value, start/
stop positions and delay factor (Read/Write) ... 17
Tab. 5.
SHIFT values .................................................. 18
Tab. 6.
PWM-Feedback registers (only Read
registers) ..........................................................19
Tab. 7.
Immediate OFF commands. Set duty cycle
to zero (Read/Write) ........................................19
Tab. 8.
Start commands for each channel (Read/
Write) ...............................................................20
Tab. 9.
Possible
identification
resistors
for
nonoverlapping ................................................21
Tab. 10. Junction temperature warning bits (Read) .......22
Tab. 11. CLEAR - CLEAR control register (address
34h) bit allocation ............................................23
Tab. 12. CLEAR - CLEAR control register (address
34h) bit description ..........................................23
Tab. 13. Open Circuit and Short Circuit registers
(Read only) ......................................................24
Tab. 14. NTC - NTC control register (address 39h) bit
allocation ......................................................... 24
Tab. 15. NTC - NTC control register (address 39h) bit
description ....................................................... 24
Tab. 16. ID - ID control register (address 3Ah) bit
allocation ......................................................... 25
Tab. 17. ID - ID control register (address 3Ah) bit
description ....................................................... 25
Tab. 18. Internal Status - Internal status control
register (address 3Bh) bit allocation ................26
Tab. 19. Internal Status - Internal status control
register (address 3Bh) bit description ..............26
Tab. 20. External charge pump capacitor selection .......27
Tab. 21. OC threshold selection and CPFSx selection
in MTP .............................................................28
Tab. 22. LHM - Limp Home mode control register
(address 3Ch) bit allocation ............................ 30
Tab. 23. LHM - Limp Home mode control register
(address 3Ch) bit description .......................... 30
Tab. 24. Limp Home mode deactivation sequence ....... 32
Tab. 25. Limp Home mode exit sequence messages ....32
Tab. 26. Standard-ID and the synchronization
sequence .........................................................33
Tab. 27. Extended-ID format ......................................... 33
Tab. 28. CAN and CAN-FD commands ........................ 34
Tab. 29. Number of Register fitting DLC (CAN - FD) .....36
Tab. 30. Standard–ID format in a response frame ........ 37
Tab. 31. ASL50xxyHz Register map ............................. 38
Tab. 32. ASL51xxSHy register map .............................. 40
Tab. 33. MLCs linked to the bits ................................... 43
Tab. 34. MTP Read/Write ..............................................44
Tab. 35. MTP memory map .......................................... 44
Tab. 36. PWM frequency selection ............................... 46
Tab. 37. Slew rate selection ..........................................46
Tab. 38. Phase shifting sequence in the different
floating blocks ................................................. 47
Tab. 39. Limp Home mode selection (58h, 59h, 5Ah
and 5Bh) ..........................................................47
Tab. 40. Short circuit timer (blanking time after duty
cycle rising edge) ............................................ 47
Tab. 41. Data rate selection .......................................... 47
Tab. 42. Open circuit (OC) threshold selection (58h,
59h, 5Ah and 5Bh) ..........................................48
Tab. 43. System configuration. Single / Multiple MLC ....48
Tab. 44. Scaling factor selection (5Ch, 5Dh, 5Eh and
5Fh) ................................................................. 48
Tab. 45. Overtemperature
warning
(OTW_x)
threshold selection .......................................... 49
Tab. 46. Partial networking selection .............................49
Tab. 47. Limiting values ................................................ 49
Tab. 48. Thermal characteristics ................................... 51
Tab. 49. Static characteristics ....................................... 51
Tab. 50. Dynamic characteristics .................................. 53
Tab. 51. Package Outline ..............................................54
Tab. 52. Revision history ...............................................65
Figures
Fig. 1.
Application diagram for the ASL5xxxyHz
family (OFF board configuration) ...................... 5
Fig. 2.
Block diagram ................................................... 6
Fig. 3.
Pin configuration for HVQFN36 .........................7
Fig. 4.
Pin configuration for LQFP48 ............................9
Fig. 5.
Single LED driving configuration application
diagram ............................................................12
Fig. 6.
Multiple strings with segment driving
configuration application diagram ....................13
Fig. 7.
Built in phase shifting sequence ......................14
Fig. 8.
Blocks of switches can be assigned to phase
shifting sequences ...........................................15
Fig. 9.
Example PWM Polynomial curves (Default
curves in MTP) ................................................16
Fig. 10.
Typical NTC resistance vs. temperature in
the range 70 °C to 130 °C .............................. 21
Fig. 11.
CAN Ext-ID frame ........................................... 33
Fig. 12.
Package outline – HVQFN package ................55
Fig. 13.
Package outline – HLQFP package ................ 60



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